SPI_DEVICE/2P Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	21.830s	4.755ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.860s	46.717us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.150s	66.036us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.170s	1.841ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.490s	4.408ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.380s	52.808us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.150s	66.036us	1	1	100.00
		spi_device_csr_aliasing	19.490s	4.408ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.650s	12.790us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.000s	37.706us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	2.190s	84.957us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	2.260s	15.100us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.940s	1.932us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.160s	69.462us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.160s	69.462us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.890s	2.613ms	1	1	100.00
		spi_device_tpm_sts_read	1.670s	127.475us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.160s	3.428ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.960s	916.548us	1	1	100.00
		spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.420s	75.161us	1	1	100.00
		spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.420s	75.161us	1	1	100.00
		spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.720s	451.606us	1	1	100.00
		spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.720s	451.606us	1	1	100.00
		spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.720s	451.606us	1	1	100.00
		spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.720s	451.606us	1	1	100.00
		spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.720s	451.606us	1	1	100.00
		spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.100s	130.642us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	9.440s	3.274ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	9.440s	3.274ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	9.440s	3.274ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.110s	649.296us	1	1	100.00
		spi_device_read_buffer_direct	11.260s	1.922ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	9.440s	3.274ms	1	1	100.00
		spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	43.400s	3.490ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.940s	290.254us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.940s	290.254us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	21.830s	4.755ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	35.830s	9.857ms	1	1	100.00
V2	stress_all	spi_device_stress_all	9.641m	417.109ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.850s	157.780us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.690s	12.806us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.930s	607.703us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.930s	607.703us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.860s	46.717us	1	1	100.00
		spi_device_csr_rw	2.150s	66.036us	1	1	100.00
		spi_device_csr_aliasing	19.490s	4.408ms	1	1	100.00
		spi_device_same_csr_outstanding	4.350s	829.389us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.860s	46.717us	1	1	100.00
		spi_device_csr_rw	2.150s	66.036us	1	1	100.00
		spi_device_csr_aliasing	19.490s	4.408ms	1	1	100.00
		spi_device_same_csr_outstanding	4.350s	829.389us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	2.130s	320.655us	1	1	100.00
		spi_device_tl_intg_err	6.500s	574.343us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.500s	574.343us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.349m	9.236ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.80687079141361817749305414807546534155146702042779712013748237086654419288757
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1149967 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1149967 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1231967 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0xb52290 [101101010010001010010000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1231967 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)