SPI_HOST Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	50.000s	7.437ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	22.247us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	18.569us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	326.121us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	101.371us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	69.986us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	18.569us	1	1	100.00
		spi_host_csr_aliasing	4.000s	101.371us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	32.832us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	42.454us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	12.000s	432.716us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	9.000s	78.754us	1	1	100.00
		spi_host_error_cmd	6.000s	17.587us	1	1	100.00
		spi_host_event	14.000s	1.236ms	1	1	100.00
V2	clock_rate	spi_host_speed	16.000s	68.127us	1	1	100.00
V2	speed	spi_host_speed	16.000s	68.127us	1	1	100.00
V2	chip_select_timing	spi_host_speed	16.000s	68.127us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	10.000s	97.166us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	238.402us	1	1	100.00
V2	cpol_cpha	spi_host_speed	16.000s	68.127us	1	1	100.00
V2	full_cycle	spi_host_speed	16.000s	68.127us	1	1	100.00
V2	duplex	spi_host_smoke	50.000s	7.437ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	50.000s	7.437ms	1	1	100.00
V2	stress_all	spi_host_stress_all	18.000s	1.203ms	1	1	100.00
V2	spien	spi_host_spien	7.000s	1.044ms	1	1	100.00
V2	stall	spi_host_status_stall	1.367m	11.780ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	16.000s	2.895ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	9.000s	78.754us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	42.862us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	30.837us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	48.520us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	48.520us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	22.247us	1	1	100.00
		spi_host_csr_rw	4.000s	18.569us	1	1	100.00
		spi_host_csr_aliasing	4.000s	101.371us	1	1	100.00
		spi_host_same_csr_outstanding	5.000s	50.392us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	22.247us	1	1	100.00
		spi_host_csr_rw	4.000s	18.569us	1	1	100.00
		spi_host_csr_aliasing	4.000s	101.371us	1	1	100.00
		spi_host_same_csr_outstanding	5.000s	50.392us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	275.280us	1	1	100.00
		spi_host_sec_cm	4.000s	142.436us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	275.280us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	29.983m	100.002ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.73897340383244854380216801428600158362381499393483271521222366254661808374377
      Line 147, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100002160263 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc64a5fd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100002160263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---