SRAM_CTRL/MAIN Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 10.650s 855.744us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.530s 18.443us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.560s 18.101us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.250s 630.187us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.660s 38.524us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.710s 485.245us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.560s 18.101us 1 1 100.00
sram_ctrl_csr_aliasing 1.660s 38.524us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 3.539m 5.257ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 1.923m 5.809ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 4.739m 3.916ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 1.583m 14.086ms 1 1 100.00
V2 bijection sram_ctrl_bijection 25.338m 40.117ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 8.624m 16.896ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 49.840s 42.362ms 1 1 100.00
V2 executable sram_ctrl_executable 7.327m 7.052ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 12.210s 1.004ms 1 1 100.00
sram_ctrl_partial_access_b2b 3.230m 4.777ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 26.510s 2.961ms 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.250s 13.476ms 1 1 100.00
sram_ctrl_throughput_w_readback 34.470s 3.818ms 1 1 100.00
V2 regwen sram_ctrl_regwen 9.549m 43.127ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.000s 1.464ms 1 1 100.00
V2 stress_all sram_ctrl_stress_all 1.113h 61.777ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.660s 153.022us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 2.560s 31.726us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 2.560s 31.726us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.530s 18.443us 1 1 100.00
sram_ctrl_csr_rw 1.560s 18.101us 1 1 100.00
sram_ctrl_csr_aliasing 1.660s 38.524us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.850s 29.026us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.530s 18.443us 1 1 100.00
sram_ctrl_csr_rw 1.560s 18.101us 1 1 100.00
sram_ctrl_csr_aliasing 1.660s 38.524us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.850s 29.026us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 39.000s 28.149ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.480s 2.066us 0 1 0.00
sram_ctrl_tl_intg_err 2.350s 354.788us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.480s 2.066us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.350s 354.788us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 9.549m 43.127ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 9.549m 43.127ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.560s 18.101us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 7.327m 7.052ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 7.327m 7.052ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 7.327m 7.052ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 49.840s 42.362ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 4.790s 2.390ms 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 39.000s 28.149ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 5.540s 665.857us 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 10.650s 855.744us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 10.650s 855.744us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 7.327m 7.052ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.480s 2.066us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 49.840s 42.362ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.480s 2.066us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.480s 2.066us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 10.650s 855.744us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.480s 2.066us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 32.510s 1.777ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets