SRAM_CTRL/RET Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.075m	4.074ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.560s	15.583us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.480s	16.045us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.150s	95.556us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.540s	13.051us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.650s	28.091us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.480s	16.045us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	13.051us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.120s	242.655us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.070s	382.065us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.830m	14.771ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.740m	4.857ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	44.720s	14.880ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.260m	3.245ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.110s	451.406us	1	1	100.00
V2	executable	sram_ctrl_executable	2.794m	1.973ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	10.560s	391.229us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.708m	8.047ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	16.480s	117.496us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	46.500s	167.630us	1	1	100.00
		sram_ctrl_throughput_w_readback	54.170s	583.339us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.411m	11.535ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.640s	89.712us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	2.341m	37.171ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.450s	95.049us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.260s	282.188us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.260s	282.188us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.560s	15.583us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	16.045us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	13.051us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	50.466us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.560s	15.583us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	16.045us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	13.051us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	50.466us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.060s	458.731us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.440s	9.627us	0	1	0.00
		sram_ctrl_tl_intg_err	2.660s	209.847us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.440s	9.627us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.660s	209.847us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.411m	11.535ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.411m	11.535ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.480s	16.045us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.794m	1.973ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.794m	1.973ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.794m	1.973ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.110s	451.406us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.530s	25.751us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.060s	458.731us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.950s	174.567us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.075m	4.074ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.075m	4.074ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.794m	1.973ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.440s	9.627us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.110s	451.406us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.440s	9.627us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.440s	9.627us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.075m	4.074ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.440s	9.627us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.770s	1.604ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.73167464858854731061472535576633909237653645738041590058369794414283750531792
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  25750536 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  25750536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.1202784757094936267784818585491203113099219904287014227413035712619101199107
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9627023 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9627023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---