SYSRST_CTRL Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 3.830s 2.132ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 6.660s 2.456ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.170s 2.445ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.360s 2.348ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 9.120s 6.030ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.330s 2.234ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.372m 39.547ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 8.780s 2.880ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 5.700s 2.066ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.330s 2.234ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.780s 2.880ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 2.929m 92.899ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 33.930s 33.089ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 3.850s 3.351ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 9.170s 4.512ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 5.620s 2.512ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 3.190s 2.106ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 17.270m 500.898ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.910s 2.622ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 5.910s 3.303ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 41.010s 40.395ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 2.196m 63.116ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 7.420s 2.014ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 3.920s 2.029ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 4.600s 2.140ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 4.600s 2.140ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 9.120s 6.030ms 1 1 100.00
sysrst_ctrl_csr_rw 2.330s 2.234ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.780s 2.880ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.000s 4.329ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 9.120s 6.030ms 1 1 100.00
sysrst_ctrl_csr_rw 2.330s 2.234ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.780s 2.880ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.000s 4.329ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 11.850s 22.115ms 1 1 100.00
sysrst_ctrl_tl_intg_err 26.350s 42.583ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 26.350s 42.583ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 8.850s 6.912ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00