UART Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	7.970s	6.332ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.450s	51.291us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.740s	17.207us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.750s	1.221ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.480s	39.882us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.730s	60.788us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.740s	17.207us	1	1	100.00
		uart_csr_aliasing	1.480s	39.882us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	4.960s	14.883ms	1	1	100.00
V2	parity	uart_smoke	7.970s	6.332ms	1	1	100.00
		uart_tx_rx	4.960s	14.883ms	1	1	100.00
V2	parity_error	uart_intr	58.180s	165.883ms	1	1	100.00
		uart_rx_parity_err	46.140s	55.076ms	1	1	100.00
V2	watermark	uart_tx_rx	4.960s	14.883ms	1	1	100.00
		uart_intr	58.180s	165.883ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.127m	120.171ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	38.090s	30.893ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	35.100s	24.899ms	1	1	100.00
V2	rx_frame_err	uart_intr	58.180s	165.883ms	1	1	100.00
V2	rx_break_err	uart_intr	58.180s	165.883ms	1	1	100.00
V2	rx_timeout	uart_intr	58.180s	165.883ms	1	1	100.00
V2	perf	uart_perf	17.617m	31.231ms	1	1	100.00
V2	sys_loopback	uart_loopback	19.220s	13.910ms	1	1	100.00
V2	line_loopback	uart_loopback	19.220s	13.910ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	24.020s	143.216ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	10.200s	4.667ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	5.430s	1.378ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	18.790s	2.882ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	17.386m	162.821ms	1	1	100.00
V2	stress_all	uart_stress_all	42.820s	42.465ms	1	1	100.00
V2	alert_test	uart_alert_test	1.940s	12.687us	1	1	100.00
V2	intr_test	uart_intr_test	1.520s	35.813us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.980s	218.725us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.980s	218.725us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.450s	51.291us	1	1	100.00
		uart_csr_rw	1.740s	17.207us	1	1	100.00
		uart_csr_aliasing	1.480s	39.882us	1	1	100.00
		uart_same_csr_outstanding	1.770s	116.192us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.450s	51.291us	1	1	100.00
		uart_csr_rw	1.740s	17.207us	1	1	100.00
		uart_csr_aliasing	1.480s	39.882us	1	1	100.00
		uart_same_csr_outstanding	1.770s	116.192us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.800s	137.592us	1	1	100.00
		uart_tl_intg_err	1.660s	54.290us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.660s	54.290us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	28.420s	2.552ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00