CHIP Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: `71732d1`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.310m	3.191ms	1	1	100.00
		chip_sw_example_rom	1.323m	2.113ms	1	1	100.00
		chip_sw_example_manufacturer	2.221m	3.033ms	1	1	100.00
		chip_sw_example_concurrency	2.322m	3.158ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.424m	5.235ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.132m	6.278ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.233m	5.228ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	51.104m	29.803ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	54.000s	2.097ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	51.104m	29.803ms	1	1	100.00
		chip_csr_rw	6.132m	6.278ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	4.770s	45.343us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.103m	4.243ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.103m	4.243ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.103m	4.243ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.417m	3.737ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.417m	3.737ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.879m	4.620ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.075m	4.528ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.808m	4.065ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.592m	4.788ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	4.676m	3.420ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.550m	9.006ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.605m	4.379ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.605m	4.379ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.459m	2.749ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.502m	5.680ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.378m	3.128ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.984m	3.265ms	1	1	100.00
		chip_tap_straps_testunlock0	4.261m	4.820ms	1	1	100.00
		chip_tap_straps_rma	1.771m	2.591ms	1	1	100.00
		chip_tap_straps_prod	12.109m	13.279ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.819m	3.183ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.262m	9.361ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.186m	5.559ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.186m	5.559ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.846m	7.778ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	18.896m	14.687ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.170m	4.434ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.398m	5.484ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.453m	18.264ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.624m	3.695ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.904m	7.191ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.359m	2.630ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.834m	10.696ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.750m	2.651ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.918m	5.033ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.948m	2.419ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.150m	3.329ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	9.515m	9.708ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.717m	4.586ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.579m	2.644ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.717m	4.586ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.382m	2.658ms	1	1	100.00
		chip_sw_aes_smoketest	2.497m	3.224ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.084m	2.326ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.901m	3.198ms	1	1	100.00
		chip_sw_csrng_smoketest	2.915m	2.344ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.315m	3.015ms	1	1	100.00
		chip_sw_gpio_smoketest	2.829m	2.987ms	1	1	100.00
		chip_sw_hmac_smoketest	3.735m	3.840ms	1	1	100.00
		chip_sw_kmac_smoketest	3.359m	3.664ms	1	1	100.00
		chip_sw_otbn_smoketest	13.680m	8.414ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.784m	5.423ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.606m	5.809ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.702m	2.664ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.577m	3.158ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.740m	2.346ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.088m	3.244ms	1	1	100.00
		chip_sw_uart_smoketest	2.589m	3.097ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.431m	2.929ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.963m	5.650ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.000h	59.967ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.325m	14.549ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.231m	5.633ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.903m	2.885ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.115m	3.015ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.836h	52.975ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.867h	55.619ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	47.480s	1.909ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	47.480s	1.909ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	51.104m	29.803ms	1	1	100.00
		chip_same_csr_outstanding	36.875m	29.820ms	1	1	100.00
		chip_csr_hw_reset	2.424m	5.235ms	1	1	100.00
		chip_csr_rw	6.132m	6.278ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	51.104m	29.803ms	1	1	100.00
		chip_same_csr_outstanding	36.875m	29.820ms	1	1	100.00
		chip_csr_hw_reset	2.424m	5.235ms	1	1	100.00
		chip_csr_rw	6.132m	6.278ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	22.500s	453.539us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.360s	48.839us	1	1	100.00
		xbar_smoke_large_delays	55.700s	9.391ms	1	1	100.00
		xbar_smoke_slow_rsp	37.270s	3.765ms	1	1	100.00
		xbar_random_zero_delays	5.010s	42.317us	1	1	100.00
		xbar_random_large_delays	3.578m	35.763ms	1	1	100.00
		xbar_random_slow_rsp	4.110m	30.521ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	12.500s	409.011us	1	1	100.00
		xbar_error_and_unmapped_addr	8.270s	100.945us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	7.840s	252.509us	1	1	100.00
		xbar_error_and_unmapped_addr	8.270s	100.945us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	57.500s	2.847ms	1	1	100.00
		xbar_access_same_device_slow_rsp	2.575m	17.593ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	12.710s	259.694us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.036m	15.178ms	1	1	100.00
		xbar_stress_all_with_error	2.436m	8.072ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	8.368m	6.553ms	1	1	100.00
		xbar_stress_all_with_reset_error	3.711m	9.585ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.325m	14.549ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	37.144m	26.451ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.792m	15.342ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.912m	11.335ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.921m	15.322ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.086m	15.675ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.394m	15.530ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.637m	14.908ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.750s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	27.680s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.500s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	26.700s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	26.450s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	25.980s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	26.390s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	25.550s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.090s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.590s	10.380us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.260s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.570s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.710s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.130s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.230s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.540s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.430s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.450s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.470s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	27.100s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.720s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.180s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.500s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	27.160s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.130s	10.260us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.045m	11.133ms	1	1	100.00
		rom_e2e_asm_init_dev	37.827m	14.637ms	1	1	100.00
		rom_e2e_asm_init_prod	36.588m	15.368ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.212m	16.140ms	1	1	100.00
		rom_e2e_asm_init_rma	37.954m	14.784ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	37.335m	14.863ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.969m	14.866ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.273m	15.101ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.945m	15.442ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.820m	19.867ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.820m	19.867ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.957m	3.067ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.624m	3.695ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.728m	2.773ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.706m	2.764ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	17.810m	9.234ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.726m	2.934ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.669m	4.361ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.575m	5.422ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.293m	5.961ms	1	1	100.00
		chip_plic_all_irqs_10	5.214m	3.960ms	1	1	100.00
		chip_plic_all_irqs_20	6.570m	4.330ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.308m	3.238ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.886m	9.049ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.431m	3.565ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	3.026m	3.138ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.435m	11.475ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	15.165m	7.643ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.645m	8.904ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.717m	7.774ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.234h	254.702ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.543m	3.661ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.784m	5.423ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.543m	3.661ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.009m	7.719ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.009m	7.719ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.037m	6.707ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.157m	5.682ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.274m	5.994ms	1	1	100.00
		chip_sw_aes_idle	2.706m	2.764ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.446m	2.471ms	1	1	100.00
		chip_sw_kmac_idle	3.177m	3.407ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.531m	3.432ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.501m	4.299ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.243m	4.555ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	5.338m	4.034ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.357m	12.779ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.527m	4.461ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.004m	4.325ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.976m	4.401ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.664m	4.968ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.518m	4.394ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.588m	4.522ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.846m	7.778ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.176m	5.906ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.976m	4.401ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.664m	4.968ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.170m	4.434ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.398m	5.484ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.453m	18.264ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.624m	3.695ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.904m	7.191ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.359m	2.630ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.834m	10.696ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.750m	2.651ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.918m	5.033ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.948m	2.419ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.259m	2.776ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.396m	4.175ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.098m	7.243ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.173m	25.755ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.099m	2.636ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.489m	2.877ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.387m	7.953ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.627m	3.492ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.009m	4.493ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.881m	19.792ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.239h	51.850ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.846m	7.778ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.392m	5.074ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.800m	3.646ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.575m	5.422ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	15.165m	7.643ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.657m	7.341ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.757m	2.870ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.346m	7.117ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.776m	2.914ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	39.130m	16.598ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.729m	2.797ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.393m	6.450ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.729m	2.797ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.657m	7.341ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.614m	2.485ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.085m	22.802ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.377m	5.561ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.398m	5.484ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.812m	4.029ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.170m	4.434ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	56.015m	44.086ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.085m	22.802ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.577m	3.451ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.697m	9.549ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.857m	3.744ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	56.015m	44.086ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.857m	3.744ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.857m	3.744ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.857m	3.744ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.857m	3.744ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.575m	5.422ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.836m	7.222ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.266m	5.439ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.385m	5.846ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.385m	5.846ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.515m	2.793ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.359m	2.630ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.446m	2.471ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.751m	3.046ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	15.250m	7.839ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.151m	4.673ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.821m	5.025ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.129m	5.139ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.304m	3.606ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.697m	9.549ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.834m	10.696ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	15.612m	7.753ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	17.810m	9.234ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	48.142m	16.173ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.798m	2.600ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.773m	2.595ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.750m	2.651ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.697m	9.549ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.627m	7.669ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.539m	2.243ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	16.001m	8.312ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.177m	3.407ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.669m	4.361ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.984m	3.265ms	1	1	100.00
		chip_tap_straps_rma	1.771m	2.591ms	1	1	100.00
		chip_tap_straps_prod	12.109m	13.279ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.528m	2.889ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.627m	7.669ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.627m	7.669ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.627m	7.669ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	18.398m	9.302ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.857m	3.744ms	1	1	100.00
		chip_sw_flash_rma_unlocked	56.015m	44.086ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.979m	3.090ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.267m	6.591ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.702m	7.183ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.425m	7.870ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.627m	7.669ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.697m	9.549ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.507m	9.239ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	4.899m	8.293ms	1	1	100.00
		chip_prim_tl_access	2.836m	7.222ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.176m	5.906ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.527m	4.461ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.004m	4.325ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.976m	4.401ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.664m	4.968ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.518m	4.394ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.588m	4.522ms	1	1	100.00
		chip_tap_straps_dev	1.984m	3.265ms	1	1	100.00
		chip_tap_straps_rma	1.771m	2.591ms	1	1	100.00
		chip_tap_straps_prod	12.109m	13.279ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.227m	11.314ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.079m	3.301ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.584m	3.276ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.714m	3.763ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.627m	3.231ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	20.082m	28.502ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.227m	11.314ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	59.166m	50.205ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.051h	49.013ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.412m	8.346ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.012h	48.285ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	20.082m	28.502ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.072m	2.559ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.181m	2.517ms	1	1	100.00
		rom_volatile_raw_unlock	1.229m	2.446ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.541m	17.367ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.453m	18.264ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.274m	5.994ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.274m	5.994ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.274m	5.994ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.356m	3.863ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.627m	7.669ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.085m	22.802ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.356m	3.863ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.697m	9.549ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.651m	4.186ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.069m	3.134ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.085m	22.802ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.356m	3.863ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.697m	9.549ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.651m	4.186ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.069m	3.134ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.627m	7.669ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.558m	4.569ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.528m	2.889ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.979m	3.090ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.267m	6.591ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.702m	7.183ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.425m	7.870ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.627m	7.669ms	1	1	100.00
		chip_prim_tl_access	2.836m	7.222ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.836m	7.222ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.824m	8.740ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.144m	5.791ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.122m	27.853ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.129m	7.482ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.546m	9.060ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	7.078m	5.828ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	10.928m	23.971ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	10.711m	14.435ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.009m	7.719ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.540m	12.013ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.258m	4.499ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.144m	5.791ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.495m	4.727ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	34.091m	33.947ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.819m	7.612ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.993m	5.474ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.678m	24.728ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.567m	6.221ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.584m	10.073ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	25.793m	30.862ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.848m	3.293ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.575m	5.422ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.507m	9.239ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.507m	9.239ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.584m	10.073ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.678m	24.728ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.258m	4.499ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.784m	5.423ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	2.960m	3.770ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.492m	4.346ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.565m	4.831ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.886m	9.049ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.647m	2.459ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.575m	5.422ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	18.645m	8.904ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.752m	4.520ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.287m	5.531ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.159m	3.221ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.069m	3.134ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.492m	4.346ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.492m	4.346ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.675m	10.849ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.844m	13.134ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	2.960m	3.770ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.324m	4.303ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.494m	5.946ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.771m	2.591ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.227m	11.314ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.293m	5.961ms	1	1	100.00
		chip_plic_all_irqs_10	5.214m	3.960ms	1	1	100.00
		chip_plic_all_irqs_20	6.570m	4.330ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.480m	2.886ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.929m	2.816ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.325m	14.549ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.217m	8.300ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.304m	3.428ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.114m	3.075ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.544m	2.930ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.651m	4.186ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.918m	5.033ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.075m	8.695ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.303m	7.121ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	4.899m	8.293ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.575m	5.422ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.186m	5.559ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.567m	6.221ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	14.542m	23.956ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.101m	2.177ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.188m	3.351ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.723m	4.834ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.542m	23.956ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.542m	23.956ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	40.973m	20.795ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	40.973m	20.795ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.034m	5.673ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.820m	19.867ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.927m	3.288ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.760m	2.903ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.396m	4.037ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.863m	3.745ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.064m	8.078ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.358h	31.245ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.212m	12.066ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.988m	2.951ms	1	1	100.00
V2		TOTAL			241	275	87.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.763m	2.851ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.941m	3.030ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.444h	72.002ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.838m	6.085ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.995m	11.591ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.814m	11.754ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.357m	12.117ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.502m	3.087ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.130m	3.407ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.228m	4.538ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	20.397s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.511m	5.032ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.524m	2.348ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.654m	4.030ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	13.736m	6.653ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.136m	2.586ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.305m	5.186ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.136m	2.788ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.539m	5.300ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.531m	6.456ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.494m	4.696ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.584m	10.073ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.995m	11.591ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.814m	11.754ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.357m	12.117ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.602m	5.043ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.575m	5.422ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.387h	38.178ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.387h	38.178ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.736m	3.900ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.417m	3.737ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	45.712m	19.488ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.270m	2.993ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.890m	5.506ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.147m	3.196ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.245m	3.237ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.834m	4.011ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.648s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.081m	2.911ms	1	1	100.00
		TOTAL			288	325	88.62

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4993172552002991683817018194533084457330407566121475295874924307598172521213
    Line 671, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.26190511698879978606885546946122139185962550664162854296163424606099049510177
    Line 732, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.37224749092495480644741493940315957266819716757452252901313404579090905831178
    Line 794, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.53877650682392193358383324490306184309557799762756591957683064631477722546730
    Line 686, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.31972604281863652951032947725721952363654144652326657559460316468003285265616
    Line 809, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.89431504427328088947930762537893927079920793730680425696471492233846893728011
    Line 642, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.51205918329203880746202695897491474806966644499953379393656320385061887847821
    Line 636, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.61964417668424951295173022602715639460451993551171207597136556829657974039215
    Line 618, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.64560487051665244820858951903144928943273540185781388951936505239189749886694
    Line 676, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.37886952790217607777974460571353128446217875134138054305510450409247418248790
    Line 627, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.26494213950164126749424171795911568927949047379141348845967922221676868801643
    Line 631, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.74590924488596008769341427124488556163845763799482737081635503946543164814991
    Line 775, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.93496445649391811051411378035454119977275657468557781967474527887276132288927
    Line 647, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.32213836458429903059289765446221639779474178567891468880624896966652213073538
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.208s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.95904842631826826334073753081040986876152939765208430111894331240040763332730
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 10.058s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.68050023355586446611745712152122630727250839282308396057476336319738712472742
    Line 901, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.85028214453397594359183665464122042568555322162516176363648339639270766088049
    Line 656, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.71880536661703155217960814669911223921872608699480502514219856139959812512389
    Line 992, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.97312231217089855862931340185502697187041648710784854224154288651626018557431
    Line 781, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.71533258744835190681704695051705574515837142218874678343077092538125184687599
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3428.459292 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3428.459292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@79349) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.112020179764957241902961384337499533550447097799344692835847817026858842425416
Line 446, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4346.429352 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@79349) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4346.429352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.7201779014509987223916515470611224514837024076164496078528988273437659283668
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2934.152862 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2934.152862 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.7663133734979462865933327636035642638955694786273562400471875285578386903835
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3137.923680 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3137.923680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:586) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.27227187273347213563438811309568945053144813381308697346333492309087900567615
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2870.343979 us: (cip_base_vseq.sv:586) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2870.343979 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32221) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.89175586527567782370333770775795776300365668926298346211034407045977282674409
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1909.142356 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32221) { a_addr: 'h10110  a_data: 'h72955293  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h4  a_user: 'h1a51b  d_param: 'h0  d_source: 'h24  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1909.142356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.105229656364792791716686555434885413815856440086954169392552765100409263997548
    Line 413, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2884.835000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2884.835000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.13111248899000808981486729205162944473863417099435033062497890525120655191169
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3014.651000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3014.651000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.63085913884724774829205812810879643673074554637780252447261747308193722650196
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 14686.544063 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 14686.544063 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.21412933718313056759458216244037499863940531177254840305690678948979007477537
    Line 798, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.89663571368594767988626835573802433554080013038564593791534466224430820149565
    Line 671, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32051) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.71384729130525057821072359948522708233633301555395697464948211403304530926496
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2097.067880 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32051) { a_addr: 'h10638  a_data: 'h55412f53  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h1b660  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2097.067880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---