ADC_CTRL Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	2.480s	5.989ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.920s	659.705us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.270s	381.908us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	24.370s	37.262ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.740s	695.653us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.560s	444.131us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.270s	381.908us	1	1	100.00
		adc_ctrl_csr_aliasing	2.740s	695.653us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	7.181m	484.583ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.663m	334.186ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	52.310s	328.313ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.285m	166.372ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	5.073m	662.757ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	18.075m	623.166ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.958m	330.670ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	38.010s	346.412ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.570s	4.473ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	14.290s	31.705ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	35.510s	90.047ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	9.933m	333.017ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.070s	568.788us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.470s	306.830us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.960s	484.449us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.960s	484.449us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.920s	659.705us	1	1	100.00
		adc_ctrl_csr_rw	2.270s	381.908us	1	1	100.00
		adc_ctrl_csr_aliasing	2.740s	695.653us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.510s	2.012ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.920s	659.705us	1	1	100.00
		adc_ctrl_csr_rw	2.270s	381.908us	1	1	100.00
		adc_ctrl_csr_aliasing	2.740s	695.653us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.510s	2.012ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	7.320s	7.634ms	1	1	100.00
		adc_ctrl_tl_intg_err	7.100s	8.362ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	7.100s	8.362ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.390s	1.646ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00