EDN Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.620s	62.651us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.600s	50.977us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.660s	28.309us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.450s	189.393us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.770s	74.550us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.920s	78.532us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.660s	28.309us	1	1	100.00
		edn_csr_aliasing	1.770s	74.550us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.920s	42.812us	1	1	100.00
V2	csrng_commands	edn_genbits	1.920s	42.812us	1	1	100.00
V2	genbits	edn_genbits	1.920s	42.812us	1	1	100.00
V2	interrupts	edn_intr	1.890s	31.729us	1	1	100.00
V2	alerts	edn_alert	1.970s	25.634us	1	1	100.00
V2	errs	edn_err	1.730s	18.685us	1	1	100.00
V2	disable	edn_disable	1.680s	35.020us	1	1	100.00
		edn_disable_auto_req_mode	1.940s	34.175us	1	1	100.00
V2	stress_all	edn_stress_all	2.160s	175.594us	1	1	100.00
V2	intr_test	edn_intr_test	1.670s	20.792us	1	1	100.00
V2	alert_test	edn_alert_test	1.780s	17.409us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.970s	67.030us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.970s	67.030us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.600s	50.977us	1	1	100.00
		edn_csr_rw	1.660s	28.309us	1	1	100.00
		edn_csr_aliasing	1.770s	74.550us	1	1	100.00
		edn_same_csr_outstanding	1.890s	56.028us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.600s	50.977us	1	1	100.00
		edn_csr_rw	1.660s	28.309us	1	1	100.00
		edn_csr_aliasing	1.770s	74.550us	1	1	100.00
		edn_same_csr_outstanding	1.890s	56.028us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.990s	317.502us	1	1	100.00
		edn_tl_intg_err	2.720s	86.439us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.740s	18.041us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.970s	25.634us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.990s	317.502us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.990s	317.502us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.990s	317.502us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.990s	317.502us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.970s	25.634us	1	1	100.00
		edn_sec_cm	4.990s	317.502us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.970s	25.634us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.720s	86.439us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	16.110s	2.170ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00