ENTROPY_SRC Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 31.144us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 39.117us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 16.667us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 13.000s 2.771ms 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 78.460us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 40.517us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 16.667us 1 1 100.00
entropy_src_csr_aliasing 7.000s 78.460us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 4.000s 31.144us 1 1 100.00
entropy_src_rng 22.000s 6.083ms 0 1 0.00
entropy_src_fw_ov 4.000s 12.096us 0 1 0.00
V2 firmware_mode entropy_src_fw_ov 4.000s 12.096us 0 1 0.00
V2 rng_mode entropy_src_rng 22.000s 6.083ms 0 1 0.00
V2 rng_max_rate entropy_src_rng_max_rate 4.000s 7.365us 0 1 0.00
V2 health_checks entropy_src_rng 22.000s 6.083ms 0 1 0.00
V2 conditioning entropy_src_rng 22.000s 6.083ms 0 1 0.00
V2 interrupts entropy_src_rng 22.000s 6.083ms 0 1 0.00
entropy_src_intr 7.000s 667.357us 1 1 100.00
V2 alerts entropy_src_rng 22.000s 6.083ms 0 1 0.00
entropy_src_functional_alerts 6.000s 120.984us 1 1 100.00
V2 stress_all entropy_src_stress_all 5.000s 72.039us 1 1 100.00
V2 functional_errors entropy_src_functional_errors 5.000s 64.328us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 6.000s 298.997us 1 1 100.00
V2 intr_test entropy_src_intr_test 4.000s 18.008us 1 1 100.00
V2 alert_test entropy_src_alert_test 4.000s 33.061us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 6.000s 125.482us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 6.000s 125.482us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 39.117us 1 1 100.00
entropy_src_csr_rw 4.000s 16.667us 1 1 100.00
entropy_src_csr_aliasing 7.000s 78.460us 1 1 100.00
entropy_src_same_csr_outstanding 5.000s 35.360us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 39.117us 1 1 100.00
entropy_src_csr_rw 4.000s 16.667us 1 1 100.00
entropy_src_csr_aliasing 7.000s 78.460us 1 1 100.00
entropy_src_same_csr_outstanding 5.000s 35.360us 1 1 100.00
V2 TOTAL 9 12 75.00
V2S tl_intg_err entropy_src_sec_cm 6.000s 314.820us 1 1 100.00
entropy_src_tl_intg_err 7.000s 186.200us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 22.000s 6.083ms 0 1 0.00
entropy_src_cfg_regwen 5.000s 57.974us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 22.000s 6.083ms 0 1 0.00
V2S sec_cm_config_redun entropy_src_rng 22.000s 6.083ms 0 1 0.00
V2S sec_cm_intersig_mubi entropy_src_rng 22.000s 6.083ms 0 1 0.00
entropy_src_fw_ov 4.000s 12.096us 0 1 0.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 5.000s 64.328us 1 1 100.00
entropy_src_sec_cm 6.000s 314.820us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 5.000s 64.328us 1 1 100.00
entropy_src_sec_cm 6.000s 314.820us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 22.000s 6.083ms 0 1 0.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 5.000s 64.328us 1 1 100.00
entropy_src_sec_cm 6.000s 314.820us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 5.000s 64.328us 1 1 100.00
entropy_src_sec_cm 6.000s 314.820us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 5.000s 64.328us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 6.000s 120.984us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 186.200us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.000s 7.424us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 18 22 81.82

Failure Buckets