HMAC Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.680s 239.974us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.890s 44.644us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.630s 142.239us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.460s 441.032us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.970s 1.044ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 10.874m 248.843ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.630s 142.239us 1 1 100.00
hmac_csr_aliasing 5.970s 1.044ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 39.980s 4.322ms 1 1 100.00
V2 back_pressure hmac_back_pressure 57.090s 10.073ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.310s 171.473us 1 1 100.00
hmac_test_sha384_vectors 19.240s 2.726ms 1 1 100.00
hmac_test_sha512_vectors 18.340s 211.453us 1 1 100.00
hmac_test_hmac256_vectors 9.720s 323.480us 1 1 100.00
hmac_test_hmac384_vectors 6.010s 177.263us 1 1 100.00
hmac_test_hmac512_vectors 13.940s 808.250us 1 1 100.00
V2 burst_wr hmac_burst_wr 17.310s 1.173ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 13.755m 6.133ms 1 1 100.00
V2 error hmac_error 22.040s 2.580ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 20.690s 3.047ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.680s 239.974us 1 1 100.00
hmac_long_msg 39.980s 4.322ms 1 1 100.00
hmac_back_pressure 57.090s 10.073ms 1 1 100.00
hmac_datapath_stress 13.755m 6.133ms 1 1 100.00
hmac_burst_wr 17.310s 1.173ms 1 1 100.00
hmac_stress_all 1.705m 3.645ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.680s 239.974us 1 1 100.00
hmac_long_msg 39.980s 4.322ms 1 1 100.00
hmac_back_pressure 57.090s 10.073ms 1 1 100.00
hmac_datapath_stress 13.755m 6.133ms 1 1 100.00
hmac_wipe_secret 20.690s 3.047ms 1 1 100.00
hmac_test_sha256_vectors 8.310s 171.473us 1 1 100.00
hmac_test_sha384_vectors 19.240s 2.726ms 1 1 100.00
hmac_test_sha512_vectors 18.340s 211.453us 1 1 100.00
hmac_test_hmac256_vectors 9.720s 323.480us 1 1 100.00
hmac_test_hmac384_vectors 6.010s 177.263us 1 1 100.00
hmac_test_hmac512_vectors 13.940s 808.250us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.680s 239.974us 1 1 100.00
hmac_long_msg 39.980s 4.322ms 1 1 100.00
hmac_back_pressure 57.090s 10.073ms 1 1 100.00
hmac_datapath_stress 13.755m 6.133ms 1 1 100.00
hmac_burst_wr 17.310s 1.173ms 1 1 100.00
hmac_error 22.040s 2.580ms 1 1 100.00
hmac_wipe_secret 20.690s 3.047ms 1 1 100.00
hmac_test_sha256_vectors 8.310s 171.473us 1 1 100.00
hmac_test_sha384_vectors 19.240s 2.726ms 1 1 100.00
hmac_test_sha512_vectors 18.340s 211.453us 1 1 100.00
hmac_test_hmac256_vectors 9.720s 323.480us 1 1 100.00
hmac_test_hmac384_vectors 6.010s 177.263us 1 1 100.00
hmac_test_hmac512_vectors 13.940s 808.250us 1 1 100.00
hmac_stress_all 1.705m 3.645ms 1 1 100.00
V2 stress_all hmac_stress_all 1.705m 3.645ms 1 1 100.00
V2 alert_test hmac_alert_test 1.400s 10.590us 1 1 100.00
V2 intr_test hmac_intr_test 1.640s 50.032us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.430s 44.386us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.430s 44.386us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.890s 44.644us 1 1 100.00
hmac_csr_rw 1.630s 142.239us 1 1 100.00
hmac_csr_aliasing 5.970s 1.044ms 1 1 100.00
hmac_same_csr_outstanding 1.860s 46.034us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.890s 44.644us 1 1 100.00
hmac_csr_rw 1.630s 142.239us 1 1 100.00
hmac_csr_aliasing 5.970s 1.044ms 1 1 100.00
hmac_same_csr_outstanding 1.860s 46.034us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.830s 158.051us 1 1 100.00
hmac_tl_intg_err 3.860s 685.824us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.860s 685.824us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.680s 239.974us 1 1 100.00
V3 stress_reset hmac_stress_reset 5.000s 289.787us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.978m 7.562ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.860s 225.190us 1 1 100.00
TOTAL 28 28 100.00