I2C Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	17.290s	1.400ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	15.080s	1.844ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.750s	25.113us	1	1	100.00
V1	csr_rw	i2c_csr_rw	2.110s	18.358us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.800s	127.943us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.790s	43.601us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.210s	29.228us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.110s	18.358us	1	1	100.00
		i2c_csr_aliasing	2.790s	43.601us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	6.050s	764.808us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	16.864m	67.768ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	33.380s	2.525ms	1	1	100.00
V2	host_override	i2c_host_override	1.620s	79.135us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.230m	8.247ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.829m	2.810ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.080s	257.774us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.070s	291.654us	1	1	100.00
		i2c_host_fifo_reset_rx	4.110s	162.771us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	31.230s	3.961ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	29.230s	5.321ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.680s	122.331us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.750s	1.769ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	7.809m	43.929ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.480s	711.058us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	56.900s	7.471ms	1	1	100.00
		i2c_target_intr_smoke	3.960s	689.963us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.810s	262.081us	1	1	100.00
		i2c_target_fifo_reset_tx	2.020s	737.124us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	11.160s	8.117ms	1	1	100.00
		i2c_target_stress_rd	56.900s	7.471ms	1	1	100.00
		i2c_target_intr_stress_wr	7.880s	4.969ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.470s	9.354ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.930s	243.185us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	6.880s	1.328ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	6.350s	10.104ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.820s	1.904ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.090s	971.565us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	33.380s	2.525ms	1	1	100.00
		i2c_host_perf_precise	3.220s	225.016us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	29.230s	5.321ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.440s	356.489us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.680s	685.951us	1	1	100.00
		i2c_target_nack_acqfull_addr	3.920s	1.004ms	1	1	100.00
		i2c_target_nack_txstretch	1.880s	137.394us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.040s	238.789us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.730s	467.590us	1	1	100.00
V2	alert_test	i2c_alert_test	1.470s	56.807us	1	1	100.00
V2	intr_test	i2c_intr_test	1.600s	22.989us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.190s	159.460us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.190s	159.460us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.750s	25.113us	1	1	100.00
		i2c_csr_rw	2.110s	18.358us	1	1	100.00
		i2c_csr_aliasing	2.790s	43.601us	1	1	100.00
		i2c_same_csr_outstanding	1.650s	54.851us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.750s	25.113us	1	1	100.00
		i2c_csr_rw	2.110s	18.358us	1	1	100.00
		i2c_csr_aliasing	2.790s	43.601us	1	1	100.00
		i2c_same_csr_outstanding	1.650s	54.851us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.730s	349.270us	1	1	100.00
		i2c_sec_cm	1.630s	172.441us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.730s	349.270us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.270s	1.025ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.640s	194.075us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.828m	600.000ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.104115628014666965734703502922501413891733771923698215681483513450526203505464
      Line 123, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 67768360990 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @18561450
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.55793041380884061352076099500355639105187465193272034442000962102451737935504
      Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 122331027 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @42975
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.46579431609256438145529667722931208600700709131623711159904500519306446706983
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 194074785 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 181 [0xb5])
        UVM_INFO @ 194074785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.113416820676911070528062914579949570296200214405238330274114178325963093644978
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10104196414 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10104196414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.87425967743951641869538580846259364228359437044624405995808801792473347672923
      Line 97, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1024943855 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1024943855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.13826505206502799407779395525142437767812420781234438778672360606511648507448
      Line 127, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.1903442436508188944085276890800944274556986743580713250496612421298912112138
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 137393673 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 137393673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---