KEYMGR Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.750s	52.436us	1	1	100.00
V1	random	keymgr_random	4.760s	895.867us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.730s	31.620us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.930s	237.706us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.930s	265.566us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.980s	723.308us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.240s	154.353us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.930s	237.706us	1	1	100.00
		keymgr_csr_aliasing	7.980s	723.308us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	7.040s	630.403us	1	1	100.00
V2	sideload	keymgr_sideload	3.350s	111.334us	1	1	100.00
		keymgr_sideload_kmac	3.450s	543.051us	1	1	100.00
		keymgr_sideload_aes	2.650s	39.004us	1	1	100.00
		keymgr_sideload_otbn	2.290s	76.613us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.850s	37.078us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	17.630s	916.140us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.710s	1.045ms	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	8.870s	865.398us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.500s	119.534us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.140s	280.444us	1	1	100.00
V2	stress_all	keymgr_stress_all	2.668m	37.901ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.560s	21.735us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.840s	78.680us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.280s	756.874us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.280s	756.874us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.730s	31.620us	1	1	100.00
		keymgr_csr_rw	1.930s	237.706us	1	1	100.00
		keymgr_csr_aliasing	7.980s	723.308us	1	1	100.00
		keymgr_same_csr_outstanding	2.620s	146.711us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.730s	31.620us	1	1	100.00
		keymgr_csr_rw	1.930s	237.706us	1	1	100.00
		keymgr_csr_aliasing	7.980s	723.308us	1	1	100.00
		keymgr_same_csr_outstanding	2.620s	146.711us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
		keymgr_tl_intg_err	1.950s	19.184us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.960s	84.863us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.960s	84.863us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.960s	84.863us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.960s	84.863us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.890s	23.914us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.950s	19.184us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.960s	84.863us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	7.040s	630.403us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.760s	895.867us	1	1	100.00
		keymgr_csr_rw	1.930s	237.706us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.760s	895.867us	1	1	100.00
		keymgr_csr_rw	1.930s	237.706us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.760s	895.867us	1	1	100.00
		keymgr_csr_rw	1.930s	237.706us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	17.630s	916.140us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.500s	119.534us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.500s	119.534us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.760s	895.867us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	4.330s	460.092us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.030s	111.242us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	17.630s	916.140us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.030s	111.242us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.030s	111.242us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.030s	111.242us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.670s	564.303us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.030s	111.242us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.870s	310.230us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.34256987321768477541003840985338379320924008150824026289014072153025639689863
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @  23913967 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @  23913967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.15982645538926397469243028333135909428506913965019248568207146177297519846621
      Line 83, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
        UVM_ERROR @  19184497 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
        UVM_INFO @  19184497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.33009078207353352867817749694459945811141712633314934164509976616071554414960
      Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
        UVM_ERROR @ 154353457 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
        UVM_INFO @ 154353457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---