PATTGEN Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: `3527f96`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	52.549us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	13.899us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	40.713us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	63.323us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	111.750us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	23.018us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	40.713us	1	1	100.00
		pattgen_csr_aliasing	4.000s	111.750us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	15.000s	1.701ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	50.000s	2.467ms	1	1	100.00
V2	error	pattgen_error	4.000s	16.417us	1	1	100.00
V2	stress_all	pattgen_stress_all	15.000s	5.928ms	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	22.611us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	14.240us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	26.873us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	26.873us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	13.899us	1	1	100.00
		pattgen_csr_rw	4.000s	40.713us	1	1	100.00
		pattgen_csr_aliasing	4.000s	111.750us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	114.008us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	13.899us	1	1	100.00
		pattgen_csr_rw	4.000s	40.713us	1	1	100.00
		pattgen_csr_aliasing	4.000s	111.750us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	114.008us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	167.718us	1	1	100.00
		pattgen_sec_cm	4.000s	238.102us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	167.718us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	1.000m	22.537ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	938.194us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:908) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.109091946357375041635438905610727727507947603911055025139774609180093387612646
Line 128, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3694524939 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3694559807 ps: (cip_base_vseq.sv:812) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3694559807 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 3694679807 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.55128849005819207555563026323008614839990752955826654572646304548502339574909
    Line 127, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 5927868541 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @11069
```