ROM_CTRL/32KB Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.990s 147.840us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.820s 132.248us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 3.670s 373.500us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.060s 208.892us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.170s 556.918us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.080s 416.538us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 3.670s 373.500us 1 1 100.00
rom_ctrl_csr_aliasing 4.170s 556.918us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.710s 215.974us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.910s 169.032us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.340s 412.123us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.280s 1.620ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.100s 567.872us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.000s 559.149us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.900s 181.694us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.900s 181.694us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.820s 132.248us 1 1 100.00
rom_ctrl_csr_rw 3.670s 373.500us 1 1 100.00
rom_ctrl_csr_aliasing 4.170s 556.918us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.160s 407.571us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.820s 132.248us 1 1 100.00
rom_ctrl_csr_rw 3.670s 373.500us 1 1 100.00
rom_ctrl_csr_aliasing 4.170s 556.918us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.160s 407.571us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 13.950s 5.851ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.504m 605.769us 1 1 100.00
rom_ctrl_tl_intg_err 43.580s 546.390us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.504m 605.769us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.504m 605.769us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.504m 605.769us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.504m 605.769us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.990s 147.840us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.990s 147.840us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.990s 147.840us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 43.580s 546.390us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.100s 567.872us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 58.010s 1.545ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 13.950s 5.851ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.504m 605.769us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.145m 6.158ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00