ROM_CTRL/64KB Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.920s 1.960ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.630s 709.211us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 8.050s 301.449us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 9.870s 1.066ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.480s 2.390ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.560s 302.055us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 8.050s 301.449us 1 1 100.00
rom_ctrl_csr_aliasing 6.480s 2.390ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.900s 298.996us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.060s 301.884us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 10.200s 1.077ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 28.760s 4.212ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.360s 1.371ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.340s 205.817us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.600s 292.908us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.600s 292.908us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.630s 709.211us 1 1 100.00
rom_ctrl_csr_rw 8.050s 301.449us 1 1 100.00
rom_ctrl_csr_aliasing 6.480s 2.390ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.260s 299.825us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.630s 709.211us 1 1 100.00
rom_ctrl_csr_rw 8.050s 301.449us 1 1 100.00
rom_ctrl_csr_aliasing 6.480s 2.390ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.260s 299.825us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 37.150s 1.632ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.412m 1.334ms 1 1 100.00
rom_ctrl_tl_intg_err 1.111m 415.346us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.412m 1.334ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.412m 1.334ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.412m 1.334ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.412m 1.334ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.920s 1.960ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.920s 1.960ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.920s 1.960ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.111m 415.346us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.360s 1.371ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.191m 5.081ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 37.150s 1.632ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.412m 1.334ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.246m 1.684ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00