RV_TIMER Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	3.550m	147.148ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.560s	19.466us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.520s	16.795us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.990s	191.106us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.540s	96.331us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.700s	276.697us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.520s	16.795us	1	1	100.00
		rv_timer_csr_aliasing	1.540s	96.331us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	38.020s	13.057ms	1	1	100.00
V2	disabled	rv_timer_disabled	40.910s	35.674ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.785m	145.556ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.785m	145.556ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.535m	176.802ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.580s	32.353us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.450s	70.297us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.450s	70.297us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.560s	19.466us	1	1	100.00
		rv_timer_csr_rw	1.520s	16.795us	1	1	100.00
		rv_timer_csr_aliasing	1.540s	96.331us	1	1	100.00
		rv_timer_same_csr_outstanding	1.450s	27.047us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.560s	19.466us	1	1	100.00
		rv_timer_csr_rw	1.520s	16.795us	1	1	100.00
		rv_timer_csr_aliasing	1.540s	96.331us	1	1	100.00
		rv_timer_same_csr_outstanding	1.450s	27.047us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.010s	207.010us	1	1	100.00
		rv_timer_tl_intg_err	2.170s	130.999us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.170s	130.999us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.780s	524.390us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			15	16	93.75

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.54938420211442975740510377919826006538192714482548454711337643515253202254770
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 524390179 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10030 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 524390179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---