SPI_DEVICE/1R1W Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.173m	65.597ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.750s	71.527us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.220s	47.225us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.240s	3.114ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.140s	848.202us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.090s	57.934us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.220s	47.225us	1	1	100.00
		spi_device_csr_aliasing	10.140s	848.202us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	2.110s	15.382us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.700s	44.593us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.640s	34.322us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.480s	21.378us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.670s	1.848us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.090s	119.921us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	6.090s	119.921us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.710s	5.177ms	1	1	100.00
		spi_device_tpm_sts_read	1.810s	44.508us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	20.270s	5.688ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.210s	2.097ms	1	1	100.00
		spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.050s	473.016us	1	1	100.00
		spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.050s	473.016us	1	1	100.00
		spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.310s	2.459ms	1	1	100.00
		spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.310s	2.459ms	1	1	100.00
		spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.310s	2.459ms	1	1	100.00
		spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.310s	2.459ms	1	1	100.00
		spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.310s	2.459ms	1	1	100.00
		spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.200s	1.885ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.840s	676.185us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.840s	676.185us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.840s	676.185us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	22.830s	12.084ms	1	1	100.00
		spi_device_read_buffer_direct	11.480s	10.736ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.840s	676.185us	1	1	100.00
		spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.780m	91.120ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.690s	192.783us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.690s	192.783us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.173m	65.597ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.210s	2.629ms	1	1	100.00
V2	stress_all	spi_device_stress_all	59.350s	42.078ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.760s	40.564us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.630s	18.902us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.210s	41.276us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.210s	41.276us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.750s	71.527us	1	1	100.00
		spi_device_csr_rw	2.220s	47.225us	1	1	100.00
		spi_device_csr_aliasing	10.140s	848.202us	1	1	100.00
		spi_device_same_csr_outstanding	2.470s	57.487us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.750s	71.527us	1	1	100.00
		spi_device_csr_rw	2.220s	47.225us	1	1	100.00
		spi_device_csr_aliasing	10.140s	848.202us	1	1	100.00
		spi_device_same_csr_outstanding	2.470s	57.487us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.260s	268.818us	1	1	100.00
		spi_device_tl_intg_err	13.570s	1.321ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.570s	1.321ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	55.520s	6.465ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.6498199826154538547996904315246229654935655297721081170985422051027531252129
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  11664047 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[41])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  11664047 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  11664047 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[937])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.114426531466718315540180199202575484214134930598915778967944251710429960924460
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1245482 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1245482 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1263482 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x97905e [100101111001000001011110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1263482 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x97905e [100101111001000001011110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])