SPI_DEVICE/2P Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	25.500s	20.553ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.120s	104.764us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.830s	18.965us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.980s	3.054ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.160s	834.951us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.470s	266.705us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.830s	18.965us	1	1	100.00
		spi_device_csr_aliasing	10.160s	834.951us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.620s	31.132us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.270s	309.344us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.830s	78.513us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.930s	85.818us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.500s	1.737us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.900s	214.673us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.900s	214.673us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.970s	801.940us	1	1	100.00
		spi_device_tpm_sts_read	1.610s	80.232us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	19.420s	18.859ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	9.830s	19.758ms	1	1	100.00
		spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.230s	18.021ms	1	1	100.00
		spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.230s	18.021ms	1	1	100.00
		spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.590s	925.521us	1	1	100.00
		spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.590s	925.521us	1	1	100.00
		spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.590s	925.521us	1	1	100.00
		spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.590s	925.521us	1	1	100.00
		spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.590s	925.521us	1	1	100.00
		spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	10.110s	4.313ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	18.530s	3.854ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	18.530s	3.854ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	18.530s	3.854ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.420s	2.958ms	1	1	100.00
		spi_device_read_buffer_direct	4.490s	11.300ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	18.530s	3.854ms	1	1	100.00
		spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	52.840s	48.289ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.460s	188.062us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.460s	188.062us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	25.500s	20.553ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.767m	41.530ms	1	1	100.00
V2	stress_all	spi_device_stress_all	21.820s	4.903ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.720s	30.115us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.540s	12.783us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.810s	501.429us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.810s	501.429us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.120s	104.764us	1	1	100.00
		spi_device_csr_rw	1.830s	18.965us	1	1	100.00
		spi_device_csr_aliasing	10.160s	834.951us	1	1	100.00
		spi_device_same_csr_outstanding	2.210s	189.071us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.120s	104.764us	1	1	100.00
		spi_device_csr_rw	1.830s	18.965us	1	1	100.00
		spi_device_csr_aliasing	10.160s	834.951us	1	1	100.00
		spi_device_same_csr_outstanding	2.210s	189.071us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	2.120s	250.093us	1	1	100.00
		spi_device_tl_intg_err	11.550s	9.181ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.550s	9.181ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.896m	70.295ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.30095737446161567532035568333360293793788856384395543574086636032004656035174
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1109910 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1109910 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1116910 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0xba48c2 [101110100100100011000010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1116910 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)