SPI_HOST Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.917m	13.273ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	35.103us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	42.810us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	469.399us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	190.892us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	45.598us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	42.810us	1	1	100.00
		spi_host_csr_aliasing	4.000s	190.892us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	123.141us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	58.245us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	30.674us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	356.035us	1	1	100.00
		spi_host_error_cmd	4.000s	17.768us	1	1	100.00
		spi_host_event	11.000s	3.428ms	1	1	100.00
V2	clock_rate	spi_host_speed	7.000s	1.012ms	1	1	100.00
V2	speed	spi_host_speed	7.000s	1.012ms	1	1	100.00
V2	chip_select_timing	spi_host_speed	7.000s	1.012ms	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	100.228us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	256.471us	1	1	100.00
V2	cpol_cpha	spi_host_speed	7.000s	1.012ms	1	1	100.00
V2	full_cycle	spi_host_speed	7.000s	1.012ms	1	1	100.00
V2	duplex	spi_host_smoke	1.917m	13.273ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.917m	13.273ms	1	1	100.00
V2	stress_all	spi_host_stress_all	2.650m	32.418ms	1	1	100.00
V2	spien	spi_host_spien	13.000s	7.134ms	1	1	100.00
V2	stall	spi_host_status_stall	24.000s	764.192us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	148.950us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	356.035us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	33.799us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	40.758us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	190.209us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	190.209us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	35.103us	1	1	100.00
		spi_host_csr_rw	4.000s	42.810us	1	1	100.00
		spi_host_csr_aliasing	4.000s	190.892us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	20.333us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	35.103us	1	1	100.00
		spi_host_csr_rw	4.000s	42.810us	1	1	100.00
		spi_host_csr_aliasing	4.000s	190.892us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	20.333us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	152.738us	1	1	100.00
		spi_host_sec_cm	3.000s	139.879us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	152.738us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	28.483m	100.004ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.58261470052819992495594947112954922689733942749009047993713611892982123408000
      Line 143, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100003663035 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd5c301d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100003663035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---