SRAM_CTRL/MAIN Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.620s	6.098ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.660s	32.506us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.090s	85.872us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.660s	497.628us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.590s	45.602us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.160s	716.980us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.090s	85.872us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	45.602us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.708m	14.271ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	56.000s	5.728ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.001m	47.732ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.476m	10.710ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	19.420m	23.937ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.101m	30.642ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	26.060s	10.903ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.434m	2.594ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	24.500s	2.490ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.794m	19.832ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	39.130s	803.690us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	12.990s	1.457ms	1	1	100.00
		sram_ctrl_throughput_w_readback	8.010s	720.798us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.408m	14.246ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.740s	346.141us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	18.870m	355.089ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	2.060s	15.441us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.210s	253.538us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.210s	253.538us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.660s	32.506us	1	1	100.00
		sram_ctrl_csr_rw	2.090s	85.872us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	45.602us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	18.956us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.660s	32.506us	1	1	100.00
		sram_ctrl_csr_rw	2.090s	85.872us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	45.602us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	18.956us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.360s	3.729ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.700s	4.178us	0	1	0.00
		sram_ctrl_tl_intg_err	3.010s	1.183ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.700s	4.178us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.010s	1.183ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.408m	14.246ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.408m	14.246ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.090s	85.872us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.434m	2.594ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.434m	2.594ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.434m	2.594ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	26.060s	10.903ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.270s	711.348us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.360s	3.729ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.800s	673.093us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.620s	6.098ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.620s	6.098ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.434m	2.594ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.700s	4.178us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	26.060s	10.903ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.700s	4.178us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.700s	4.178us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.620s	6.098ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.700s	4.178us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.119m	6.170ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.38292718767515854406469338628310708610516710616370150912183744736615606835696
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4177907 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4177907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---