SRAM_CTRL/RET Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.650s	1.151ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.920s	70.314us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.710s	50.008us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.960s	1.351ms	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.610s	36.325us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.630s	117.563us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.710s	50.008us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	36.325us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.240s	291.316us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.090s	277.039us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.410m	10.823ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.427m	23.343ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	22.200s	3.959ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.237m	2.608ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.670s	599.784us	1	1	100.00
V2	executable	sram_ctrl_executable	5.815m	5.912ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.670s	2.194ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.610m	82.560ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.090s	176.759us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	16.110s	115.983us	1	1	100.00
		sram_ctrl_throughput_w_readback	52.720s	304.280us	1	1	100.00
V2	regwen	sram_ctrl_regwen	15.496m	35.008ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.720s	30.270us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	3.231m	2.886ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.500s	26.361us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.960s	156.889us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.960s	156.889us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.920s	70.314us	1	1	100.00
		sram_ctrl_csr_rw	1.710s	50.008us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	36.325us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	51.427us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.920s	70.314us	1	1	100.00
		sram_ctrl_csr_rw	1.710s	50.008us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	36.325us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	51.427us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.290s	409.641us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.540s	1.221us	0	1	0.00
		sram_ctrl_tl_intg_err	3.020s	293.684us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.540s	1.221us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.020s	293.684us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	15.496m	35.008ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	15.496m	35.008ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.710s	50.008us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.815m	5.912ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.815m	5.912ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.815m	5.912ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.670s	599.784us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.780s	60.945us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.290s	409.641us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.800s	82.828us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.650s	1.151ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.650s	1.151ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.815m	5.912ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.540s	1.221us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.670s	599.784us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.540s	1.221us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.540s	1.221us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.650s	1.151ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.540s	1.221us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.137m	4.619ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.35786187884079261159547923637644199921977951682579023216691907305875237243590
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1220761 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1220761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---