SYSRST_CTRL Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	5.280s	2.112ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	2.630s	2.480ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.220s	2.194ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.730s	2.516ms	0	1	0.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	4.080s	6.088ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	1.880s	2.197ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	38.090s	74.834ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	6.170s	2.084ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	5.760s	2.045ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	1.880s	2.197ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.170s	2.084ms	1	1	100.00
V1		TOTAL			8	9	88.89
V2	combo_detect	sysrst_ctrl_combo_detect	3.780m	124.365ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	20.490s	56.205ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	10.010s	3.485ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	5.760s	2.477ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	4.070s	2.520ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.080s	2.233ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	6.080s	3.035ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.010s	2.707ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.480s	7.938ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	36.040s	33.145ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	8.740s	7.462ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	3.560s	2.021ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.510s	2.061ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.170s	2.331ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.170s	2.331ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	4.080s	6.088ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.880s	2.197ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.170s	2.084ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.320s	4.482ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	4.080s	6.088ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.880s	2.197ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.170s	2.084ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.320s	4.482ms	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	11.170s	22.167ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	7.700s	43.117ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	7.700s	43.117ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	10.450s	5.250ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:
  • Test sysrst_ctrl_combo_detect_ec_rst_with_pre_cond has 1 failures.

    • 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.44544884332312197831978323966124160037392471419078586943281148616693705350741
      Line 381, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest/run.log

        UVM_ERROR @ 2291818570 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
        UVM_INFO @ 2515638248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---