UART Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: 3527f96

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.800s	456.260us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.610s	46.941us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.450s	24.067us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.100s	1.042ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.820s	57.004us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.820s	192.799us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.450s	24.067us	1	1	100.00
		uart_csr_aliasing	1.820s	57.004us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	35.060s	35.161ms	1	1	100.00
V2	parity	uart_smoke	2.800s	456.260us	1	1	100.00
		uart_tx_rx	35.060s	35.161ms	1	1	100.00
V2	parity_error	uart_intr	6.610s	5.261ms	1	1	100.00
		uart_rx_parity_err	13.670s	19.799ms	1	1	100.00
V2	watermark	uart_tx_rx	35.060s	35.161ms	1	1	100.00
		uart_intr	6.610s	5.261ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.147m	65.369ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	22.810s	91.872ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	2.059m	37.556ms	1	1	100.00
V2	rx_frame_err	uart_intr	6.610s	5.261ms	1	1	100.00
V2	rx_break_err	uart_intr	6.610s	5.261ms	1	1	100.00
V2	rx_timeout	uart_intr	6.610s	5.261ms	1	1	100.00
V2	perf	uart_perf	13.125m	22.842ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.170s	1.422ms	1	1	100.00
V2	line_loopback	uart_loopback	3.170s	1.422ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.174m	181.525ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.730s	3.495ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	5.130s	13.393ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	19.580s	3.105ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.185m	57.679ms	1	1	100.00
V2	stress_all	uart_stress_all	56.530s	396.603ms	1	1	100.00
V2	alert_test	uart_alert_test	2.010s	130.074us	1	1	100.00
V2	intr_test	uart_intr_test	1.610s	43.808us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.100s	222.674us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.100s	222.674us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.610s	46.941us	1	1	100.00
		uart_csr_rw	1.450s	24.067us	1	1	100.00
		uart_csr_aliasing	1.820s	57.004us	1	1	100.00
		uart_same_csr_outstanding	1.880s	113.523us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.610s	46.941us	1	1	100.00
		uart_csr_rw	1.450s	24.067us	1	1	100.00
		uart_csr_aliasing	1.820s	57.004us	1	1	100.00
		uart_same_csr_outstanding	1.880s	113.523us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.760s	34.815us	1	1	100.00
		uart_tl_intg_err	1.890s	189.404us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.890s	189.404us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.160s	7.160ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00