CHIP Simulation Results

Tuesday April 15 2025 18:35:32 UTC

GitHub Revision: `3527f96`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.959m	2.585ms	1	1	100.00
		chip_sw_example_rom	1.337m	2.527ms	1	1	100.00
		chip_sw_example_manufacturer	1.594m	1.901ms	1	1	100.00
		chip_sw_example_concurrency	1.934m	2.152ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.920m	6.830ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.603m	4.069ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.424m	5.940ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	50.913m	27.944ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	56.240s	2.254ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	50.913m	27.944ms	1	1	100.00
		chip_csr_rw	2.603m	4.069ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.010s	39.720us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.185m	4.207ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.185m	4.207ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.185m	4.207ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.822m	3.675ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.822m	3.675ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.757m	4.256ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.218m	3.665ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.099m	5.027ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.058m	3.344ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.345m	8.924ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	17.361m	13.813ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.156m	5.348ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.156m	5.348ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.044m	3.692ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.409m	3.013ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.219m	2.537ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	8.905m	9.186ms	1	1	100.00
		chip_tap_straps_testunlock0	6.543m	6.731ms	1	1	100.00
		chip_tap_straps_rma	2.141m	3.238ms	1	1	100.00
		chip_tap_straps_prod	9.403m	9.081ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.908m	2.976ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.960m	7.812ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.531m	4.532ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.531m	4.532ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.925m	8.109ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	24.079m	16.464ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.173m	3.956ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.497m	6.030ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.027m	19.297ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.901m	3.268ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.855m	6.299ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.623m	2.999ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.957m	7.062ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.712m	3.482ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.406m	4.601ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.697m	2.718ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.225m	3.238ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.747m	8.116ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.531m	5.615ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.720m	3.078ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.531m	5.615ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.335m	2.877ms	1	1	100.00
		chip_sw_aes_smoketest	2.700m	3.231ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.979m	3.481ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.542m	3.019ms	1	1	100.00
		chip_sw_csrng_smoketest	2.320m	3.006ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.209m	4.221ms	1	1	100.00
		chip_sw_gpio_smoketest	2.456m	3.034ms	1	1	100.00
		chip_sw_hmac_smoketest	3.025m	2.940ms	1	1	100.00
		chip_sw_kmac_smoketest	2.818m	2.901ms	1	1	100.00
		chip_sw_otbn_smoketest	11.383m	6.549ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.799m	6.508ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.850m	5.781ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.094m	2.449ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.334m	2.985ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.922m	2.389ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.126m	2.714ms	1	1	100.00
		chip_sw_uart_smoketest	2.086m	2.499ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.833m	2.857ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.331m	4.879ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.997h	61.268ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.338m	14.665ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.206m	4.272ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.735m	3.069ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.784m	3.011ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.736h	54.004ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.835h	56.055ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	44.580s	2.481ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	44.580s	2.481ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	50.913m	27.944ms	1	1	100.00
		chip_same_csr_outstanding	41.091m	33.195ms	1	1	100.00
		chip_csr_hw_reset	3.920m	6.830ms	1	1	100.00
		chip_csr_rw	2.603m	4.069ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	50.913m	27.944ms	1	1	100.00
		chip_same_csr_outstanding	41.091m	33.195ms	1	1	100.00
		chip_csr_hw_reset	3.920m	6.830ms	1	1	100.00
		chip_csr_rw	2.603m	4.069ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	7.510s	95.781us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.810s	37.490us	1	1	100.00
		xbar_smoke_large_delays	34.800s	5.853ms	1	1	100.00
		xbar_smoke_slow_rsp	51.760s	6.102ms	1	1	100.00
		xbar_random_zero_delays	17.670s	305.373us	1	1	100.00
		xbar_random_large_delays	34.230s	5.607ms	1	1	100.00
		xbar_random_slow_rsp	1.636m	10.936ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	24.120s	937.694us	1	1	100.00
		xbar_error_and_unmapped_addr	11.110s	347.706us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	46.340s	1.976ms	1	1	100.00
		xbar_error_and_unmapped_addr	11.110s	347.706us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.234m	2.888ms	1	1	100.00
		xbar_access_same_device_slow_rsp	6.963m	49.538ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	10.620s	216.663us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.423m	4.311ms	1	1	100.00
		xbar_stress_all_with_error	1.164m	2.873ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.560s	9.780us	1	1	100.00
		xbar_stress_all_with_reset_error	1.654m	4.093ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.338m	14.665ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	35.461m	28.722ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.624m	15.076ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.217m	10.399ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	38.924m	15.970ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	38.550m	15.609ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.179m	15.173ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.763m	15.081ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.070s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	28.180s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	28.580s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	31.070s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.290s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.030s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.140s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.530s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.830s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	26.760s	10.320us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.290s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.330s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.530s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.120s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.560s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.500s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.640s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.020s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.700s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.450s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.430s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.470s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.500s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	27.050s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	28.440s	10.140us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.913m	11.510ms	1	1	100.00
		rom_e2e_asm_init_dev	38.743m	15.542ms	1	1	100.00
		rom_e2e_asm_init_prod	39.309m	15.366ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.860m	16.104ms	1	1	100.00
		rom_e2e_asm_init_rma	36.231m	15.589ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.643m	15.063ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	34.649m	14.256ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.715m	14.227ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	39.187m	16.459ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.985m	19.197ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.985m	19.197ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.238m	2.511ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.901m	3.268ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.704m	2.268ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.035m	2.861ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	20.512m	10.675ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.411m	3.058ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.595m	4.976ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.818m	4.699ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.904m	5.363ms	1	1	100.00
		chip_plic_all_irqs_10	4.585m	4.117ms	1	1	100.00
		chip_plic_all_irqs_20	6.168m	4.917ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.913m	3.371ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.168m	10.688ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.405m	4.887ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.930m	3.109ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	8.659m	8.823ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	19.153m	9.504ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.316m	7.833ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.630m	8.000ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.908h	254.583ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.115m	3.504ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.799m	6.508ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.115m	3.504ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.739m	10.510ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.739m	10.510ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.678m	6.337ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.234m	5.243ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.862m	5.598ms	1	1	100.00
		chip_sw_aes_idle	3.035m	2.861ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.749m	2.968ms	1	1	100.00
		chip_sw_kmac_idle	2.482m	3.166ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.737m	5.011ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	2.889m	4.476ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.524m	4.744ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.465m	5.053ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.103m	11.529ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.116m	4.120ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.277m	4.918ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.092m	4.399ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.683m	5.037ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.095m	4.124ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.913m	4.783ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.925m	8.109ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	9.523m	9.215ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.092m	4.399ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.683m	5.037ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.173m	3.956ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.497m	6.030ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.027m	19.297ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.901m	3.268ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.855m	6.299ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.623m	2.999ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.957m	7.062ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.712m	3.482ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.406m	4.601ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.697m	2.718ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.225m	2.905ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.505m	4.243ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.133m	7.627ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.303m	25.402ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.434m	3.397ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.379m	2.901ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	17.762m	12.348ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.022m	3.901ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.272m	4.944ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.826m	24.611ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.640h	124.101ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.925m	8.109ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.190m	4.329ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.473m	3.282ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.818m	4.699ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	19.153m	9.504ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.693m	7.524ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.070m	2.603ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.902m	7.588ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.834m	3.088ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.269h	30.880ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.960m	3.057ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.569m	6.261ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.960m	3.057ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.693m	7.524ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.971m	2.273ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.828m	23.071ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.296m	5.304ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.497m	6.030ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.880m	4.328ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.173m	3.956ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	58.815m	43.582ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.828m	23.071ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.980m	2.866ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	22.462m	11.967ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.872m	4.323ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	58.815m	43.582ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.872m	4.323ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.872m	4.323ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.872m	4.323ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.872m	4.323ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.818m	4.699ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.594m	11.695ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.142m	5.285ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.242m	4.920ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.242m	4.920ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.974m	2.681ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.623m	2.999ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.749m	2.968ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.031m	3.005ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	15.294m	7.858ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.676m	5.116ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.999m	4.566ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.068m	6.166ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.769m	4.130ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	22.462m	11.967ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.957m	7.062ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	23.301m	9.739ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	20.512m	10.675ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	37.380m	11.085ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.074m	2.761ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.726m	3.352ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.712m	3.482ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	22.462m	11.967ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.116m	10.990ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.425m	3.372ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	10.639m	5.491ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.482m	3.166ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.595m	4.976ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	8.905m	9.186ms	1	1	100.00
		chip_tap_straps_rma	2.141m	3.238ms	1	1	100.00
		chip_tap_straps_prod	9.403m	9.081ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.148m	3.249ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.116m	10.990ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.116m	10.990ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.116m	10.990ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	19.380m	11.363ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.872m	4.323ms	1	1	100.00
		chip_sw_flash_rma_unlocked	58.815m	43.582ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.442m	3.063ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.885m	6.940ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.738m	5.200ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.486m	6.831ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.116m	10.990ms	1	1	100.00
		chip_sw_keymgr_key_derivation	22.462m	11.967ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.794m	9.033ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.460m	8.179ms	1	1	100.00
		chip_prim_tl_access	4.594m	11.695ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	9.523m	9.215ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.116m	4.120ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.277m	4.918ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.092m	4.399ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.683m	5.037ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.095m	4.124ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.913m	4.783ms	1	1	100.00
		chip_tap_straps_dev	8.905m	9.186ms	1	1	100.00
		chip_tap_straps_rma	2.141m	3.238ms	1	1	100.00
		chip_tap_straps_prod	9.403m	9.081ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.906m	17.668ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.064m	4.208ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.480m	2.995ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.297m	2.348ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.145m	3.256ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.443m	29.378ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.906m	17.668ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.043h	48.845ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	59.430m	47.987ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.775m	8.287ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.345m	45.064ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.443m	29.378ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.334m	2.873ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.262m	2.478ms	1	1	100.00
		rom_volatile_raw_unlock	1.245m	2.422ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.959m	17.398ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.027m	19.297ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.862m	5.598ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.862m	5.598ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.862m	5.598ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.978m	3.766ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.116m	10.990ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.828m	23.071ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.978m	3.766ms	1	1	100.00
		chip_sw_keymgr_key_derivation	22.462m	11.967ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.859m	5.345ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.246m	2.563ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.828m	23.071ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.978m	3.766ms	1	1	100.00
		chip_sw_keymgr_key_derivation	22.462m	11.967ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.859m	5.345ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.246m	2.563ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.116m	10.990ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.140m	4.852ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.148m	3.249ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.442m	3.063ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.885m	6.940ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.738m	5.200ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.486m	6.831ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.116m	10.990ms	1	1	100.00
		chip_prim_tl_access	4.594m	11.695ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.594m	11.695ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.670m	8.582ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.882m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	12.083m	25.442ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.075m	7.926ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.774m	10.399ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.895m	6.975ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.091m	23.133ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.902m	15.058ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.739m	10.510ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.022m	14.078ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.872m	4.469ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.882m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.306m	4.686ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.363m	31.994ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.924m	5.402ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.474m	5.178ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.876m	27.544ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.901m	8.987ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.021m	9.130ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	26.283m	29.230ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.805m	3.080ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.818m	4.699ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.794m	9.033ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.794m	9.033ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.021m	9.130ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.876m	27.544ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.872m	4.469ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.799m	6.508ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.751m	3.835ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.070m	3.385ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.715m	4.926ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.168m	10.688ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.415m	3.089ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.818m	4.699ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.316m	7.833ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.786m	4.880ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.098m	4.855ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.721m	2.939ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.246m	2.563ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.070m	3.385ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.070m	3.385ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	20.752m	22.265ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.806m	13.539ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.751m	3.835ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.705m	4.732ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.087m	6.289ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.141m	3.238ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.906m	17.668ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.904m	5.363ms	1	1	100.00
		chip_plic_all_irqs_10	4.585m	4.117ms	1	1	100.00
		chip_plic_all_irqs_20	6.168m	4.917ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.128m	2.642ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.015m	3.009ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.338m	14.665ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.925m	7.441ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.524m	3.032ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.304m	3.906ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.822m	2.963ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.859m	5.345ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.406m	4.601ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.236m	8.305ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.464m	7.847ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.460m	8.179ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.818m	4.699ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.531m	4.532ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.901m	8.987ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.501m	22.170ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.173m	2.502ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.864m	3.366ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.998m	5.155ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.501m	22.170ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.501m	22.170ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	37.498m	20.207ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	37.498m	20.207ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.677m	5.579ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	6.985m	19.197ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.739m	2.936ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.708m	2.837ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.353m	3.239ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.478m	4.179ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.303m	7.965ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.303h	31.691ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.259m	11.794ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.952m	3.294ms	1	1	100.00
V2		TOTAL			241	275	87.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.410m	3.074ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.965m	3.212ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.375h	71.747ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.912m	6.081ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.692m	11.415ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.824m	11.787ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.793m	10.155ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.361m	4.169ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.630m	4.440ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.784m	4.624ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.683s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.346m	5.109ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.725m	2.382ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.218m	4.365ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	12.293m	6.941ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.590m	2.797ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.412m	5.628ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.184m	2.859ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.789m	6.157ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.732m	4.883ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.782m	4.847ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.021m	9.130ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.692m	11.415ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.824m	11.787ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.793m	10.155ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.313m	4.308ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.818m	4.699ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.420h	38.388ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.420h	38.388ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.447m	2.823ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	4.822m	3.675ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.882m	19.100ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.435m	2.598ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.350m	5.964ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.883m	2.672ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.482m	2.586ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.391m	4.336ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.434s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.127m	3.061ms	1	1	100.00
		TOTAL			288	325	88.62

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.9278796737386896326657002457645904004041735438682961443827060653120842287751
    Line 652, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.34761690291520472537918012056260060057321985474219014842973873525590481071591
    Line 735, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1362427743485909437332552854282411581295530533628798023314801750987435847603
    Line 685, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.25433667415681358068365121061944295138009853740285605067345642715197762781119
    Line 813, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.44315103796573982578279697742861674944272037136830249658164464248585843146327
    Line 696, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.105420081076305890277060468387467029586195775174364539390398467122826427278438
    Line 576, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.110939089761253996502181771791416667872662799300376030956162821512682282013833
    Line 629, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.54986326673898262811660954831054481705884241448394878375663564579598445276692
    Line 607, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.90130177750027290538328988715704318985366082080081242195813971506523865204768
    Line 610, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.18980097469217664213652173282410185730691604342153708193289911634052220498909
    Line 659, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.23097204383490102063453323460981468119627656612815221231855849428391452538352
    Line 597, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.62129405675451273883755120814121556253996186453981838722882281921076734841493
    Line 691, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.58769533331465503993277278663375052051679482073062212052308496012762587175335
    Line 649, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.30139345456984409597971705554898344645072033384419883307683154981697101152552
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.837s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.8230743284269152377550546343574752437691738321103044217609395656265123626186
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.156s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.58294885520097863538709218213978750505647562327534024239207141512751976520958
    Line 821, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.84565455959084640635249740064460013725977328443825414818613483174882426007572
    Line 704, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.39104845457276877199664281090638947285183215271811916409110642600905053934157
    Line 855, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.5213329190004891327185274831113435360864125818940759720081512468716380070722
    Line 802, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.108674150192999577408073136564078015668783738075532480564121309238324341554151
    Line 426, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3031.764080 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3031.764080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@112837) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.64842667015290868138556995554672713976256602829378371206991942448654090149024
Line 458, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3385.240416 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@112837) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3385.240416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.56802773745147546196190243778812568722786894233114955262355893117876818217596
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3057.961308 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3057.961308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.7914246367696027659546812587918248762669515658786520515227065006749713631845
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3109.395308 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3109.395308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:586) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.81832796409911030684332528427425911270045537881648230948396753887913076695324
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2602.756306 us: (cip_base_vseq.sv:586) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2602.756306 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33477) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.105024642835833765561981250418442179376985333026742111047895290448346307774854
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2481.240632 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33477) { a_addr: 'h10468  a_data: 'h194f194a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h4  a_user: 'h1b119  d_param: 'h0  d_source: 'h24  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2481.240632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.24214373727938481776051176691220086035430934549263403634368940956346503732384
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3069.383000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3069.383000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.84640940495063244916774829960728651356161964530902168278371367013539634307950
    Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3011.438000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3011.438000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.19136925440972457722078871088226010476228852396475704390777081820048508825950
    Line 443, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 16464.176581 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 16464.176581 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.16486669834538567679722100579882588906169680862551499161328240963865790185540
    Line 728, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.74569843001923485317789495096314995727304272180165373856312514408821406468638
    Line 632, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32305) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.17232465921680933722219722515279528217130706643702167139014701790414168415107
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2253.628814 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32305) { a_addr: 'h104d4  a_data: 'h5f9babbf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h1a5d0  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2253.628814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---