ADC_CTRL Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	8.890s	6.130ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.790s	792.292us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.190s	558.203us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.125m	27.239ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.190s	832.752us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.860s	435.759us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.190s	558.203us	1	1	100.00
		adc_ctrl_csr_aliasing	3.190s	832.752us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.563m	494.966ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.434m	161.145ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1.297m	161.332ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.628m	498.400ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.569m	372.692ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.421m	397.039ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.496m	325.034ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	6.479m	513.555ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	8.430s	4.194ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	6.000s	22.759ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.576m	67.770ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	3.935m	379.964ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.740s	387.275us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.090s	374.627us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.220s	440.140us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.220s	440.140us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.790s	792.292us	1	1	100.00
		adc_ctrl_csr_rw	2.190s	558.203us	1	1	100.00
		adc_ctrl_csr_aliasing	3.190s	832.752us	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.880s	4.155ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.790s	792.292us	1	1	100.00
		adc_ctrl_csr_rw	2.190s	558.203us	1	1	100.00
		adc_ctrl_csr_aliasing	3.190s	832.752us	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.880s	4.155ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.130s	8.376ms	1	1	100.00
		adc_ctrl_tl_intg_err	15.100s	8.103ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	15.100s	8.103ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.954m	10.000s	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.adc_ctrl_stress_all_with_rand_reset.87290796602609821595804215772506039598780702101720843860655463287795893099298
      Line 240, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---