EDN Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.650s	28.928us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.730s	19.499us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.700s	14.715us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.350s	170.377us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.650s	18.146us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.730s	42.292us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.700s	14.715us	1	1	100.00
		edn_csr_aliasing	1.650s	18.146us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	3.810s	305.469us	1	1	100.00
V2	csrng_commands	edn_genbits	3.810s	305.469us	1	1	100.00
V2	genbits	edn_genbits	3.810s	305.469us	1	1	100.00
V2	interrupts	edn_intr	1.610s	70.640us	1	1	100.00
V2	alerts	edn_alert	1.770s	37.040us	1	1	100.00
V2	errs	edn_err	1.800s	44.545us	1	1	100.00
V2	disable	edn_disable	1.700s	50.644us	1	1	100.00
		edn_disable_auto_req_mode	1.690s	43.709us	1	1	100.00
V2	stress_all	edn_stress_all	4.310s	234.158us	1	1	100.00
V2	intr_test	edn_intr_test	1.780s	44.706us	1	1	100.00
V2	alert_test	edn_alert_test	1.640s	31.285us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.620s	479.421us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.620s	479.421us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.730s	19.499us	1	1	100.00
		edn_csr_rw	1.700s	14.715us	1	1	100.00
		edn_csr_aliasing	1.650s	18.146us	1	1	100.00
		edn_same_csr_outstanding	2.030s	134.595us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.730s	19.499us	1	1	100.00
		edn_csr_rw	1.700s	14.715us	1	1	100.00
		edn_csr_aliasing	1.650s	18.146us	1	1	100.00
		edn_same_csr_outstanding	2.030s	134.595us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.320s	481.695us	1	1	100.00
		edn_tl_intg_err	2.590s	380.498us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.620s	14.955us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.770s	37.040us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.320s	481.695us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.320s	481.695us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.320s	481.695us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.320s	481.695us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.770s	37.040us	1	1	100.00
		edn_sec_cm	4.320s	481.695us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.770s	37.040us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.590s	380.498us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.144m	4.514ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00