HMAC Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.080s 1.029ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.850s 120.946us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.590s 17.441us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.800s 368.160us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.010s 61.069us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.630s 18.738us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.590s 17.441us 1 1 100.00
hmac_csr_aliasing 3.010s 61.069us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 6.180s 2.102ms 1 1 100.00
V2 back_pressure hmac_back_pressure 31.620s 2.313ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.724m 49.407ms 1 1 100.00
hmac_test_sha384_vectors 18.900s 255.214us 1 1 100.00
hmac_test_sha512_vectors 6.513m 13.726ms 1 1 100.00
hmac_test_hmac256_vectors 7.750s 233.538us 1 1 100.00
hmac_test_hmac384_vectors 6.710s 624.963us 1 1 100.00
hmac_test_hmac512_vectors 10.520s 2.693ms 1 1 100.00
V2 burst_wr hmac_burst_wr 7.370s 4.558ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.367m 4.665ms 1 1 100.00
V2 error hmac_error 58.290s 5.761ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 23.800s 1.217ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.080s 1.029ms 1 1 100.00
hmac_long_msg 6.180s 2.102ms 1 1 100.00
hmac_back_pressure 31.620s 2.313ms 1 1 100.00
hmac_datapath_stress 2.367m 4.665ms 1 1 100.00
hmac_burst_wr 7.370s 4.558ms 1 1 100.00
hmac_stress_all 27.710s 4.318ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.080s 1.029ms 1 1 100.00
hmac_long_msg 6.180s 2.102ms 1 1 100.00
hmac_back_pressure 31.620s 2.313ms 1 1 100.00
hmac_datapath_stress 2.367m 4.665ms 1 1 100.00
hmac_wipe_secret 23.800s 1.217ms 1 1 100.00
hmac_test_sha256_vectors 2.724m 49.407ms 1 1 100.00
hmac_test_sha384_vectors 18.900s 255.214us 1 1 100.00
hmac_test_sha512_vectors 6.513m 13.726ms 1 1 100.00
hmac_test_hmac256_vectors 7.750s 233.538us 1 1 100.00
hmac_test_hmac384_vectors 6.710s 624.963us 1 1 100.00
hmac_test_hmac512_vectors 10.520s 2.693ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.080s 1.029ms 1 1 100.00
hmac_long_msg 6.180s 2.102ms 1 1 100.00
hmac_back_pressure 31.620s 2.313ms 1 1 100.00
hmac_datapath_stress 2.367m 4.665ms 1 1 100.00
hmac_burst_wr 7.370s 4.558ms 1 1 100.00
hmac_error 58.290s 5.761ms 1 1 100.00
hmac_wipe_secret 23.800s 1.217ms 1 1 100.00
hmac_test_sha256_vectors 2.724m 49.407ms 1 1 100.00
hmac_test_sha384_vectors 18.900s 255.214us 1 1 100.00
hmac_test_sha512_vectors 6.513m 13.726ms 1 1 100.00
hmac_test_hmac256_vectors 7.750s 233.538us 1 1 100.00
hmac_test_hmac384_vectors 6.710s 624.963us 1 1 100.00
hmac_test_hmac512_vectors 10.520s 2.693ms 1 1 100.00
hmac_stress_all 27.710s 4.318ms 1 1 100.00
V2 stress_all hmac_stress_all 27.710s 4.318ms 1 1 100.00
V2 alert_test hmac_alert_test 1.280s 43.227us 1 1 100.00
V2 intr_test hmac_intr_test 1.460s 57.882us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.990s 311.804us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.990s 311.804us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.850s 120.946us 1 1 100.00
hmac_csr_rw 1.590s 17.441us 1 1 100.00
hmac_csr_aliasing 3.010s 61.069us 1 1 100.00
hmac_same_csr_outstanding 1.830s 21.107us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.850s 120.946us 1 1 100.00
hmac_csr_rw 1.590s 17.441us 1 1 100.00
hmac_csr_aliasing 3.010s 61.069us 1 1 100.00
hmac_same_csr_outstanding 1.830s 21.107us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.690s 337.852us 1 1 100.00
hmac_tl_intg_err 2.280s 339.606us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.280s 339.606us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.080s 1.029ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.840s 421.457us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.080m 10.631ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.390s 31.980us 1 1 100.00
TOTAL 28 28 100.00