I2C Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: `d6a1303`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	15.110s	1.167ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	13.540s	1.337ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.570s	26.515us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.590s	29.734us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.680s	65.669us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.840s	192.695us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.640s	51.046us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.590s	29.734us	1	1	100.00
		i2c_csr_aliasing	1.840s	192.695us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.970s	87.040us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	13.119m	58.489ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	3.071m	17.809ms	1	1	100.00
V2	host_override	i2c_host_override	1.670s	24.695us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.741m	12.152ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	41.720s	2.357ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.870s	119.067us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.030s	364.635us	1	1	100.00
		i2c_host_fifo_reset_rx	2.620s	110.951us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.404m	10.777ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	19.200s	1.313ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.480s	190.782us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.180s	2.390ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	50.920s	12.907ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.270s	3.023ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	6.210s	3.858ms	1	1	100.00
		i2c_target_intr_smoke	4.120s	1.729ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.800s	367.989us	1	1	100.00
		i2c_target_fifo_reset_tx	2.120s	212.756us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	6.290s	14.699ms	1	1	100.00
		i2c_target_stress_rd	6.210s	3.858ms	1	1	100.00
		i2c_target_intr_stress_wr	12.650s	15.002ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.960s	5.375ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.960s	198.881us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.420s	3.591ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.480s	320.088us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.220s	3.817ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.740s	132.560us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	3.071m	17.809ms	1	1	100.00
		i2c_host_perf_precise	31.730s	2.456ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	19.200s	1.313ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.900s	553.104us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.820s	1.929ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.710s	602.454us	1	1	100.00
		i2c_target_nack_txstretch	2.040s	294.856us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	13.040s	925.335us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.350s	2.089ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.570s	17.061us	1	1	100.00
V2	intr_test	i2c_intr_test	1.440s	29.802us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.090s	312.542us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.090s	312.542us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.570s	26.515us	1	1	100.00
		i2c_csr_rw	1.590s	29.734us	1	1	100.00
		i2c_csr_aliasing	1.840s	192.695us	1	1	100.00
		i2c_same_csr_outstanding	1.790s	32.599us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.570s	26.515us	1	1	100.00
		i2c_csr_rw	1.590s	29.734us	1	1	100.00
		i2c_csr_aliasing	1.840s	192.695us	1	1	100.00
		i2c_same_csr_outstanding	1.790s	32.599us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	1.940s	56.639us	1	1	100.00
		i2c_sec_cm	1.600s	129.631us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.940s	56.639us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	21.150s	1.382ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.210s	936.342us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	19.780s	740.623us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.39326227031711874252856396761763182694193985837647712848194352511420467350032
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1382044246 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1382044246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.97057637223373832310160320867704085305145727251401970620290427768923911486895
    Line 86, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 740622885 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 740622885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.72175624799961995038516681402897624873086844082016962612234550389615100953250
Line 214, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 58488677257 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13414202

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.78386613961106767351814843729763354728871117302558330745035724675072750209371
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 936342212 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 195 [0xc3])
  UVM_INFO @ 936342212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.74984340264688995871769144535113780447133748930793413366737977444811270105882
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 190781993 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x50648e94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 190781993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```