KEYMGR Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: `d6a1303`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	17.270s	884.521us	1	1	100.00
V1	random	keymgr_random	10.600s	2.177ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.820s	15.225us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.580s	11.556us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.810s	539.631us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	3.080s	740.946us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.530s	257.243us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.580s	11.556us	1	1	100.00
		keymgr_csr_aliasing	3.080s	740.946us	0	1	0.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	3.400s	186.799us	1	1	100.00
V2	sideload	keymgr_sideload	2.710s	474.797us	1	1	100.00
		keymgr_sideload_kmac	3.410s	52.103us	1	1	100.00
		keymgr_sideload_aes	2.360s	79.957us	1	1	100.00
		keymgr_sideload_otbn	5.670s	1.788ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.740s	211.601us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.700s	56.136us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.030s	59.238us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.530s	903.390us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.270s	72.039us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.130s	131.294us	1	1	100.00
V2	stress_all	keymgr_stress_all	31.260s	2.353ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.820s	18.784us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.840s	20.176us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.470s	55.636us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.470s	55.636us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.820s	15.225us	1	1	100.00
		keymgr_csr_rw	1.580s	11.556us	1	1	100.00
		keymgr_csr_aliasing	3.080s	740.946us	0	1	0.00
		keymgr_same_csr_outstanding	2.550s	79.202us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.820s	15.225us	1	1	100.00
		keymgr_csr_rw	1.580s	11.556us	1	1	100.00
		keymgr_csr_aliasing	3.080s	740.946us	0	1	0.00
		keymgr_same_csr_outstanding	2.550s	79.202us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
		keymgr_tl_intg_err	5.230s	102.233us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.190s	194.217us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.190s	194.217us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.190s	194.217us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.190s	194.217us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.180s	2.537ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.230s	102.233us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.190s	194.217us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.400s	186.799us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	10.600s	2.177ms	1	1	100.00
		keymgr_csr_rw	1.580s	11.556us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	10.600s	2.177ms	1	1	100.00
		keymgr_csr_rw	1.580s	11.556us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	10.600s	2.177ms	1	1	100.00
		keymgr_csr_rw	1.580s	11.556us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.700s	56.136us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.270s	72.039us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.270s	72.039us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	10.600s	2.177ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	6.510s	436.054us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.930s	257.339us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.700s	56.136us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.930s	257.339us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.930s	257.339us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.930s	257.339us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.770s	589.221us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.930s	257.339us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	5.860s	887.740us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test keymgr_csr_bit_bash has 1 failures.

0.keymgr_csr_bit_bash.5694693428351765389067091236784246439748565806839570879079005287320468657565
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 539630863 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 539630863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_aliasing has 1 failures.

0.keymgr_csr_aliasing.91422251409259571315957152169299399370240130363676850672698045638911902519391
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @ 740946362 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @ 740946362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:907) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 0.keymgr_stress_all_with_rand_reset.30736142445698811896977963947616563495661936592571699522905011379912582577507
    Line 542, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 887740290 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 887740290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```