KMAC/MASKED Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	43.040s	6.593ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.930s	23.652us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.950s	57.003us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.080s	8.943ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.750s	555.896us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.340s	30.616us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.950s	57.003us	1	1	100.00
		kmac_csr_aliasing	4.750s	555.896us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.640s	121.520us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.300s	24.739us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	21.860s	1.671ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.291m	54.229ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.875m	331.200ms	1	1	100.00
		kmac_test_vectors_sha3_256	32.253m	89.373ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.795m	182.996ms	1	1	100.00
		kmac_test_vectors_sha3_512	18.051m	48.810ms	1	1	100.00
		kmac_test_vectors_shake_128	3.493m	66.788ms	1	1	100.00
		kmac_test_vectors_shake_256	29.958m	239.334ms	1	1	100.00
		kmac_test_vectors_kmac	2.640s	113.034us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.710s	177.161us	1	1	100.00
V2	sideload	kmac_sideload	3.202m	19.626ms	1	1	100.00
V2	app	kmac_app	3.186m	19.507ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.919m	27.722ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.276m	16.146ms	1	1	100.00
V2	error	kmac_error	4.214m	13.510ms	1	1	100.00
V2	key_error	kmac_key_error	9.950s	1.508ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.280s	207.263us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.630s	779.773us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.910s	556.694us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	50.940s	10.026ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.130s	38.685us	1	1	100.00
V2	stress_all	kmac_stress_all	4.981m	5.822ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.540s	12.970us	1	1	100.00
V2	alert_test	kmac_alert_test	2.050s	31.607us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.580s	144.738us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.580s	144.738us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.930s	23.652us	1	1	100.00
		kmac_csr_rw	1.950s	57.003us	1	1	100.00
		kmac_csr_aliasing	4.750s	555.896us	1	1	100.00
		kmac_same_csr_outstanding	2.240s	172.374us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.930s	23.652us	1	1	100.00
		kmac_csr_rw	1.950s	57.003us	1	1	100.00
		kmac_csr_aliasing	4.750s	555.896us	1	1	100.00
		kmac_same_csr_outstanding	2.240s	172.374us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.350s	415.873us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.350s	415.873us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.350s	415.873us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.350s	415.873us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.720s	36.529us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	1.020m	20.491ms	1	1	100.00
		kmac_tl_intg_err	1.800s	18.107us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.800s	18.107us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.130s	38.685us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	43.040s	6.593ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.202m	19.626ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.350s	415.873us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.020m	20.491ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.020m	20.491ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.020m	20.491ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	43.040s	6.593ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.130s	38.685us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.020m	20.491ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.625m	3.063ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	43.040s	6.593ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.223m	71.071ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.8764607439635354899104725460270971486361300221453153986630962268512354581414
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
        UVM_ERROR @  36529237 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
        UVM_INFO @  36529237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.39930940494168548356621726120745830586818656134936191332889319407672624190198
      Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @  18107185 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @  18107185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---