KMAC/UNMASKED Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	16.770s	1.897ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.930s	102.724us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.910s	48.103us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.820s	4.831ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.940s	272.049us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.170s	50.923us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.910s	48.103us	1	1	100.00
		kmac_csr_aliasing	3.940s	272.049us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.570s	30.797us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.070s	21.088us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.057m	32.201ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.252m	10.841ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	18.417m	17.668ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.640s	602.642us	1	1	100.00
		kmac_test_vectors_sha3_384	17.870s	2.287ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.510s	2.780ms	1	1	100.00
		kmac_test_vectors_shake_128	32.692m	429.029ms	1	1	100.00
		kmac_test_vectors_shake_256	1.157m	3.225ms	1	1	100.00
		kmac_test_vectors_kmac	2.580s	64.611us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.150s	222.249us	1	1	100.00
V2	sideload	kmac_sideload	1.033m	1.140ms	1	1	100.00
V2	app	kmac_app	8.570s	182.360us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.219m	26.043ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	17.710s	1.183ms	1	1	100.00
V2	error	kmac_error	42.130s	2.184ms	1	1	100.00
V2	key_error	kmac_key_error	3.620s	514.567us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.880s	18.411us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.580s	1.070ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	21.870s	4.908ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	33.500s	6.161ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	5.140s	964.098us	1	1	100.00
V2	stress_all	kmac_stress_all	12.540s	1.635ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.530s	76.505us	1	1	100.00
V2	alert_test	kmac_alert_test	1.760s	56.873us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.270s	62.411us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.270s	62.411us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.930s	102.724us	1	1	100.00
		kmac_csr_rw	1.910s	48.103us	1	1	100.00
		kmac_csr_aliasing	3.940s	272.049us	1	1	100.00
		kmac_same_csr_outstanding	2.610s	114.378us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.930s	102.724us	1	1	100.00
		kmac_csr_rw	1.910s	48.103us	1	1	100.00
		kmac_csr_aliasing	3.940s	272.049us	1	1	100.00
		kmac_same_csr_outstanding	2.610s	114.378us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.740s	300.064us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.740s	300.064us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.740s	300.064us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.740s	300.064us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.100s	756.099us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	54.400s	48.182ms	1	1	100.00
		kmac_tl_intg_err	3.710s	94.912us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.710s	94.912us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	5.140s	964.098us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	16.770s	1.897ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.033m	1.140ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.740s	300.064us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.400s	48.182ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.400s	48.182ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.400s	48.182ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	16.770s	1.897ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	5.140s	964.098us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.400s	48.182ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.355m	6.149ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	16.770s	1.897ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	57.880s	3.167ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.80434833746784092968862010742916327103326708965980139818167744867741150415204
      Line 133, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3167450911 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3167450911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---