PATTGEN Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	16.000s	28.376us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	7.000s	30.875us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	6.000s	20.924us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	7.000s	252.678us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	5.000s	17.552us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	5.000s	58.968us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	6.000s	20.924us	1	1	100.00
		pattgen_csr_aliasing	5.000s	17.552us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	16.000s	35.409us	1	1	100.00
V2	cnt_rollover	cnt_rollover	32.000s	2.045ms	1	1	100.00
V2	error	pattgen_error	16.000s	25.265us	1	1	100.00
V2	stress_all	pattgen_stress_all	13.000s	112.208us	0	1	0.00
V2	alert_test	pattgen_alert_test	12.000s	28.319us	1	1	100.00
V2	intr_test	pattgen_intr_test	8.000s	36.296us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	12.000s	333.786us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	12.000s	333.786us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	7.000s	30.875us	1	1	100.00
		pattgen_csr_rw	6.000s	20.924us	1	1	100.00
		pattgen_csr_aliasing	5.000s	17.552us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	16.787us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	7.000s	30.875us	1	1	100.00
		pattgen_csr_rw	6.000s	20.924us	1	1	100.00
		pattgen_csr_aliasing	5.000s	17.552us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	16.787us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	11.000s	131.198us	1	1	100.00
		pattgen_sec_cm	14.000s	350.666us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	11.000s	131.198us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	33.000s	2.740ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	15.000s	446.692us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:908) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.112778948337214841007753963132973894286844372575075836127564213315826261303316
      Line 203, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 960653963 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 960657216 ps: (cip_base_vseq.sv:812) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 960657216 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 3/5
        UVM_INFO @ 960709846 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.19974642744262843318212149464072916723952668875401445870098894240842659549414
      Line 127, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @ 112207920 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ------------------------------------
        Name      Type          Size  Value
        ------------------------------------
        exp_item  pattgen_item  -     @10321