ROM_CTRL/32KB Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.790s 357.331us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.290s 575.375us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.710s 500.486us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.530s 163.814us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.550s 924.492us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.330s 1.225ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.710s 500.486us 1 1 100.00
rom_ctrl_csr_aliasing 4.550s 924.492us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.750s 293.422us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.050s 186.030us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.790s 230.656us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 15.470s 6.362ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.210s 272.978us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.150s 166.395us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.370s 1.027ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.370s 1.027ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.290s 575.375us 1 1 100.00
rom_ctrl_csr_rw 5.710s 500.486us 1 1 100.00
rom_ctrl_csr_aliasing 4.550s 924.492us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.090s 174.762us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.290s 575.375us 1 1 100.00
rom_ctrl_csr_rw 5.710s 500.486us 1 1 100.00
rom_ctrl_csr_aliasing 4.550s 924.492us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.090s 174.762us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.580s 844.773us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.101m 666.187us 1 1 100.00
rom_ctrl_tl_intg_err 40.390s 1.162ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.101m 666.187us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.101m 666.187us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.101m 666.187us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.101m 666.187us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.790s 357.331us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.790s 357.331us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.790s 357.331us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 40.390s 1.162ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.210s 272.978us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.323m 1.954ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.580s 844.773us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.101m 666.187us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 5.734m 19.037ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00