ROM_CTRL/64KB Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.360s 1.071ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.010s 1.039ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.310s 1.029ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.850s 1.028ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.890s 578.348us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.950s 1.573ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.310s 1.029ms 1 1 100.00
rom_ctrl_csr_aliasing 6.890s 578.348us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 8.530s 4.151ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.100s 207.314us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.170s 312.679us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 26.090s 3.018ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.640s 1.425ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 8.650s 1.065ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.640s 1.024ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.640s 1.024ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.010s 1.039ms 1 1 100.00
rom_ctrl_csr_rw 7.310s 1.029ms 1 1 100.00
rom_ctrl_csr_aliasing 6.890s 578.348us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.730s 534.383us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.010s 1.039ms 1 1 100.00
rom_ctrl_csr_rw 7.310s 1.029ms 1 1 100.00
rom_ctrl_csr_aliasing 6.890s 578.348us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.730s 534.383us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.850s 5.976ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.582m 10.998ms 1 1 100.00
rom_ctrl_tl_intg_err 1.113m 840.069us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.582m 10.998ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.582m 10.998ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.582m 10.998ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.582m 10.998ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.360s 1.071ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.360s 1.071ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.360s 1.071ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.113m 840.069us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.640s 1.425ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.637m 7.742ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.850s 5.976ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.582m 10.998ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 34.730s 2.588ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00