RV_DM/USE_JTAG_INTERFACE Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.930s 1.074ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.800s 619.339us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.050s 157.562us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 12.100s 6.084ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.830s 476.056us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 13.460s 5.590ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 6.040s 2.460ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 4.310s 2.661ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.462m 49.167ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.640s 830.716us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.630s 236.219us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.520s 459.215us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.550s 212.871us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.540s 111.093us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.210s 1.005ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.610s 165.511us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.730s 330.541us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.640s 830.716us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.720s 86.919us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.750s 211.452us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.520s 459.215us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.670s 97.397us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.830s 189.829us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 3.150s 220.652us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 24.260s 11.145ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 54.810s 50.578ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.840s 54.455us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 54.810s 50.578ms 1 1 100.00
rv_dm_csr_rw 3.150s 220.652us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.660s 137.076us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.570s 123.767us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 1.930s 1.074ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.850s 259.588us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.010s 335.847us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.620s 133.286us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.060s 787.290us 1 1 100.00
V2 sba rv_dm_sba_tl_access 6.530s 2.727ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.890s 465.008us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 2.370s 1.512ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 9.080s 14.167ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.520s 673.198us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.090s 730.875us 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 3.220s 800.845us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.470s 170.200us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 12.650s 13.418ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 1.670s 45.451us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.470s 86.408us 1 1 100.00
V2 stress_all rv_dm_stress_all 6.490s 4.460ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.910s 91.883us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.510s 53.406us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.510s 53.406us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 54.810s 50.578ms 1 1 100.00
rv_dm_csr_hw_reset 2.830s 189.829us 1 1 100.00
rv_dm_csr_rw 3.150s 220.652us 1 1 100.00
rv_dm_same_csr_outstanding 6.990s 646.251us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 54.810s 50.578ms 1 1 100.00
rv_dm_csr_hw_reset 2.830s 189.829us 1 1 100.00
rv_dm_csr_rw 3.150s 220.652us 1 1 100.00
rv_dm_same_csr_outstanding 6.990s 646.251us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.330s 772.695us 1 1 100.00
rv_dm_tl_intg_err 7.980s 5.425ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 7.980s 5.425ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.090s 730.875us 1 1 100.00
rv_dm_debug_disabled 1.690s 68.217us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.090s 730.875us 1 1 100.00
rv_dm_debug_disabled 1.690s 68.217us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 1.930s 1.074ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.980s 437.483us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.030s 260.650us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.030s 260.650us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.980s 437.483us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.500s 53.745us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.520s 29.010us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets