SPI_DEVICE/1R1W Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.262m	46.334ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.570s	29.725us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.640s	111.561us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.770s	387.248us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.370s	1.733ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.530s	501.817us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.640s	111.561us	1	1	100.00
		spi_device_csr_aliasing	11.370s	1.733ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.450s	16.111us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.490s	233.287us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.560s	27.343us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.350s	2.678us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.440s	3.290us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.660s	74.759us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.660s	74.759us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.960s	3.274ms	1	1	100.00
		spi_device_tpm_sts_read	1.780s	98.440us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.620s	16.300ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	20.420s	9.447ms	1	1	100.00
		spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.190s	2.128ms	1	1	100.00
		spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.190s	2.128ms	1	1	100.00
		spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.180s	1.008ms	1	1	100.00
		spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.180s	1.008ms	1	1	100.00
		spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.180s	1.008ms	1	1	100.00
		spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.180s	1.008ms	1	1	100.00
		spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.180s	1.008ms	1	1	100.00
		spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.000s	629.487us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	47.900s	9.962ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	47.900s	9.962ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	47.900s	9.962ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	12.690s	10.110ms	1	1	100.00
		spi_device_read_buffer_direct	3.800s	5.810ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	47.900s	9.962ms	1	1	100.00
		spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.542m	53.527ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.200s	221.427us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.200s	221.427us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.262m	46.334ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.301m	96.881ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.641m	87.126ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.600s	21.812us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.500s	12.013us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.200s	52.661us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.200s	52.661us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.570s	29.725us	1	1	100.00
		spi_device_csr_rw	2.640s	111.561us	1	1	100.00
		spi_device_csr_aliasing	11.370s	1.733ms	1	1	100.00
		spi_device_same_csr_outstanding	2.160s	65.165us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.570s	29.725us	1	1	100.00
		spi_device_csr_rw	2.640s	111.561us	1	1	100.00
		spi_device_csr_aliasing	11.370s	1.733ms	1	1	100.00
		spi_device_same_csr_outstanding	2.160s	65.165us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.930s	181.392us	1	1	100.00
		spi_device_tl_intg_err	12.980s	311.176us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.980s	311.176us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.182m	58.345ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.100979568639014213452254666624257352246552346240436923673998690289312567965425
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2317697 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[35])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2317697 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2317697 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[931])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.59688507460729844859176581364151730565156113912743098680064567094706412269171
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2425003 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2425003 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   2517003 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2a790 [101010011110010000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   2517003 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x2a790 [101010011110010000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])