SPI_DEVICE/2P Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.977m	146.750ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.000s	80.753us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.400s	134.846us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.190s	192.230us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.640s	310.914us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.880s	535.178us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.400s	134.846us	1	1	100.00
		spi_device_csr_aliasing	15.640s	310.914us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	2.110s	11.224us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.190s	23.632us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.780s	17.809us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.780s	120.033us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.770s	17.467us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	5.270s	473.455us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	5.270s	473.455us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.150s	818.455us	1	1	100.00
		spi_device_tpm_sts_read	1.760s	27.180us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.120s	9.936ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.800s	424.625us	1	1	100.00
		spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.690s	378.621us	1	1	100.00
		spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.690s	378.621us	1	1	100.00
		spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.120s	163.736us	1	1	100.00
		spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.120s	163.736us	1	1	100.00
		spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.120s	163.736us	1	1	100.00
		spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.120s	163.736us	1	1	100.00
		spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.120s	163.736us	1	1	100.00
		spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	13.600s	7.246ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	13.480s	4.558ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	13.480s	4.558ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	13.480s	4.558ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	17.090s	2.688ms	1	1	100.00
		spi_device_read_buffer_direct	6.960s	4.869ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	13.480s	4.558ms	1	1	100.00
		spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.840s	17.358us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	17.070s	19.543ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	17.070s	19.543ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.977m	146.750ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.538m	137.554ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.308m	67.050ms	1	1	100.00
V2	alert_test	spi_device_alert_test	2.040s	13.303us	1	1	100.00
V2	intr_test	spi_device_intr_test	2.230s	30.860us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.280s	918.063us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.280s	918.063us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.000s	80.753us	1	1	100.00
		spi_device_csr_rw	2.400s	134.846us	1	1	100.00
		spi_device_csr_aliasing	15.640s	310.914us	1	1	100.00
		spi_device_same_csr_outstanding	2.900s	318.964us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.000s	80.753us	1	1	100.00
		spi_device_csr_rw	2.400s	134.846us	1	1	100.00
		spi_device_csr_aliasing	15.640s	310.914us	1	1	100.00
		spi_device_same_csr_outstanding	2.900s	318.964us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	2.320s	158.617us	1	1	100.00
		spi_device_tl_intg_err	14.080s	1.105ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.080s	1.105ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.411m	149.619ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.25547289861850265648751560009903067399006404669777124807569020090116125958514
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @  16640017 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  16640017 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @  16661017 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x25e531 [1001011110010100110001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @  16661017 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)