SPI_HOST Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.783m	16.989ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	20.199us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	20.815us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	927.855us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	55.951us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	37.073us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	20.815us	1	1	100.00
		spi_host_csr_aliasing	4.000s	55.951us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	14.101us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	43.128us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	104.517us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	33.000s	3.669ms	1	1	100.00
		spi_host_error_cmd	3.000s	44.482us	1	1	100.00
		spi_host_event	7.000s	286.729us	1	1	100.00
V2	clock_rate	spi_host_speed	14.000s	372.279us	1	1	100.00
V2	speed	spi_host_speed	14.000s	372.279us	1	1	100.00
V2	chip_select_timing	spi_host_speed	14.000s	372.279us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	16.000s	730.524us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	118.503us	1	1	100.00
V2	cpol_cpha	spi_host_speed	14.000s	372.279us	1	1	100.00
V2	full_cycle	spi_host_speed	14.000s	372.279us	1	1	100.00
V2	duplex	spi_host_smoke	1.783m	16.989ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.783m	16.989ms	1	1	100.00
V2	stress_all	spi_host_stress_all	51.000s	2.949ms	1	1	100.00
V2	spien	spi_host_spien	6.000s	929.966us	1	1	100.00
V2	stall	spi_host_status_stall	18.000s	1.981ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	210.055us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	33.000s	3.669ms	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	51.926us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	49.315us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	214.355us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	214.355us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	20.199us	1	1	100.00
		spi_host_csr_rw	4.000s	20.815us	1	1	100.00
		spi_host_csr_aliasing	4.000s	55.951us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	41.128us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	20.199us	1	1	100.00
		spi_host_csr_rw	4.000s	20.815us	1	1	100.00
		spi_host_csr_aliasing	4.000s	55.951us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	41.128us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	791.163us	1	1	100.00
		spi_host_sec_cm	4.000s	83.803us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	791.163us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	22.467m	99.508ms	1	1	100.00
		TOTAL			26	26	100.00