SRAM_CTRL/MAIN Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	57.980s	988.481us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.560s	15.326us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.500s	15.214us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.720s	1.292ms	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.480s	19.362us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.880s	368.641us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.500s	15.214us	1	1	100.00
		sram_ctrl_csr_aliasing	1.480s	19.362us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.702m	14.135ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.480m	8.293ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.399m	35.902ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.999m	6.136ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.390m	36.201ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.079m	23.171ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	44.450s	25.091ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.704m	19.230ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	18.440s	1.694ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.886m	20.058ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	6.940s	2.521ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	16.630s	14.351ms	1	1	100.00
		sram_ctrl_throughput_w_readback	5.250s	1.157ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.500m	14.739ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.230s	741.788us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	42.991m	183.926ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.550s	15.107us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.930s	96.054us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.930s	96.054us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.560s	15.326us	1	1	100.00
		sram_ctrl_csr_rw	1.500s	15.214us	1	1	100.00
		sram_ctrl_csr_aliasing	1.480s	19.362us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	33.271us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.560s	15.326us	1	1	100.00
		sram_ctrl_csr_rw	1.500s	15.214us	1	1	100.00
		sram_ctrl_csr_aliasing	1.480s	19.362us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	33.271us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	15.980s	3.885ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.460s	7.817us	0	1	0.00
		sram_ctrl_tl_intg_err	2.760s	436.110us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.460s	7.817us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.760s	436.110us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.500m	14.739ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.500m	14.739ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.500s	15.214us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.704m	19.230ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.704m	19.230ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.704m	19.230ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	44.450s	25.091ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.650s	727.448us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	15.980s	3.885ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.830s	702.057us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	57.980s	988.481us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	57.980s	988.481us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.704m	19.230ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.460s	7.817us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	44.450s	25.091ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.460s	7.817us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.460s	7.817us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	57.980s	988.481us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.460s	7.817us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	32.010s	7.137ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.35676038024280352203552224353219355630573732414807152684067866610886155147656
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   7816946 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   7816946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---