SRAM_CTRL/RET Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 3.880s 76.585us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.510s 14.367us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.510s 13.460us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.800s 89.425us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.500s 17.521us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 1.760s 103.984us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.510s 13.460us 1 1 100.00
sram_ctrl_csr_aliasing 1.500s 17.521us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 4.160s 156.883us 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 4.260s 67.161us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 10.451m 4.397ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 3.300m 6.198ms 1 1 100.00
V2 bijection sram_ctrl_bijection 12.740s 2.237ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 8.171m 5.579ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.950s 1.798ms 1 1 100.00
V2 executable sram_ctrl_executable 9.564m 3.474ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 6.830s 83.231us 1 1 100.00
sram_ctrl_partial_access_b2b 4.923m 15.973ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 25.750s 383.017us 1 1 100.00
sram_ctrl_throughput_w_partial_write 41.910s 169.627us 1 1 100.00
sram_ctrl_throughput_w_readback 22.530s 236.960us 1 1 100.00
V2 regwen sram_ctrl_regwen 7.544m 20.306ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 1.610s 28.773us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 8.937m 62.689ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.630s 16.468us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 2.410s 212.324us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 2.410s 212.324us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.510s 14.367us 1 1 100.00
sram_ctrl_csr_rw 1.510s 13.460us 1 1 100.00
sram_ctrl_csr_aliasing 1.500s 17.521us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.620s 13.481us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.510s 14.367us 1 1 100.00
sram_ctrl_csr_rw 1.510s 13.460us 1 1 100.00
sram_ctrl_csr_aliasing 1.500s 17.521us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.620s 13.481us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.210s 1.439ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.500s 5.030us 0 1 0.00
sram_ctrl_tl_intg_err 2.180s 122.538us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.500s 5.030us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.180s 122.538us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 7.544m 20.306ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 7.544m 20.306ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.510s 13.460us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 9.564m 3.474ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 9.564m 3.474ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 9.564m 3.474ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.950s 1.798ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 1.630s 126.262us 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.210s 1.439ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 1.810s 99.766us 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 3.880s 76.585us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 3.880s 76.585us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 9.564m 3.474ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.500s 5.030us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.950s 1.798ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.500s 5.030us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.500s 5.030us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 3.880s 76.585us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.500s 5.030us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 1.131m 617.258us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets