SYSRST_CTRL Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.190s 2.143ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 6.560s 2.466ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 5.600s 2.210ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.770s 2.395ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 7.040s 4.044ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 5.220s 2.041ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 3.716m 68.647ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 7.930s 2.505ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 1.980s 2.294ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 5.220s 2.041ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.930s 2.505ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 36.250s 69.374ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 11.540s 23.857ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.403m 300.897ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 6.080s 5.878ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 6.730s 2.510ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 7.100s 2.195ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 6.580s 2.704ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.340s 2.612ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 4.810s 4.918ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 19.430s 39.159ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 8.210s 12.389ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.510s 2.024ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 5.300s 2.011ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 6.340s 2.031ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 6.340s 2.031ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 7.040s 4.044ms 1 1 100.00
sysrst_ctrl_csr_rw 5.220s 2.041ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.930s 2.505ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.160s 7.485ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 7.040s 4.044ms 1 1 100.00
sysrst_ctrl_csr_rw 5.220s 2.041ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.930s 2.505ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.160s 7.485ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 13.080s 22.077ms 1 1 100.00
sysrst_ctrl_tl_intg_err 12.350s 22.272ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 12.350s 22.272ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 11.330s 3.656ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00