UART Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: d6a1303

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.910s	458.023us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.510s	16.518us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.570s	40.523us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.080s	123.407us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.570s	19.800us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.810s	81.330us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.570s	40.523us	1	1	100.00
		uart_csr_aliasing	1.570s	19.800us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	9.300s	79.685ms	1	1	100.00
V2	parity	uart_smoke	1.910s	458.023us	1	1	100.00
		uart_tx_rx	9.300s	79.685ms	1	1	100.00
V2	parity_error	uart_intr	1.017m	44.957ms	1	1	100.00
		uart_rx_parity_err	46.550s	55.929ms	1	1	100.00
V2	watermark	uart_tx_rx	9.300s	79.685ms	1	1	100.00
		uart_intr	1.017m	44.957ms	1	1	100.00
V2	fifo_full	uart_fifo_full	47.470s	113.024ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	9.780s	34.730ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	14.970s	45.306ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.017m	44.957ms	1	1	100.00
V2	rx_break_err	uart_intr	1.017m	44.957ms	1	1	100.00
V2	rx_timeout	uart_intr	1.017m	44.957ms	1	1	100.00
V2	perf	uart_perf	5.737m	11.233ms	1	1	100.00
V2	sys_loopback	uart_loopback	7.540s	10.442ms	1	1	100.00
V2	line_loopback	uart_loopback	7.540s	10.442ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	26.850s	26.795ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	8.460s	48.075ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.580s	7.724ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.670s	4.859ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	11.537m	148.576ms	1	1	100.00
V2	stress_all	uart_stress_all	51.710s	153.875ms	1	1	100.00
V2	alert_test	uart_alert_test	1.660s	25.748us	1	1	100.00
V2	intr_test	uart_intr_test	1.530s	40.851us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.310s	256.220us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.310s	256.220us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.510s	16.518us	1	1	100.00
		uart_csr_rw	1.570s	40.523us	1	1	100.00
		uart_csr_aliasing	1.570s	19.800us	1	1	100.00
		uart_same_csr_outstanding	1.720s	145.215us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.510s	16.518us	1	1	100.00
		uart_csr_rw	1.570s	40.523us	1	1	100.00
		uart_csr_aliasing	1.570s	19.800us	1	1	100.00
		uart_same_csr_outstanding	1.720s	145.215us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.830s	72.019us	1	1	100.00
		uart_tl_intg_err	1.910s	64.056us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.910s	64.056us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	24.390s	2.103ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00