CHIP Simulation Results

Wednesday April 16 2025 20:16:05 UTC

GitHub Revision: `d6a1303`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.927m	2.803ms	1	1	100.00
		chip_sw_example_rom	1.112m	2.286ms	1	1	100.00
		chip_sw_example_manufacturer	2.393m	2.876ms	1	1	100.00
		chip_sw_example_concurrency	1.810m	2.889ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.667m	6.017ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.259m	3.879ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	8.210m	8.567ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.152h	37.292ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	8.789m	12.305ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.152h	37.292ms	1	1	100.00
		chip_csr_rw	3.259m	3.879ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.200s	47.573us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.121m	4.481ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.121m	4.481ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.121m	4.481ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.779m	4.018ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.779m	4.018ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.043m	4.250ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.302m	3.922ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.295m	4.195ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.048m	7.582ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	18.033m	8.642ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.341m	8.073ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.239m	4.375ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.239m	4.375ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.082m	3.479ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.747m	3.233ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.285m	4.185ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.793m	2.661ms	1	1	100.00
		chip_tap_straps_testunlock0	10.000m	10.065ms	1	1	100.00
		chip_tap_straps_rma	3.391m	3.846ms	1	1	100.00
		chip_tap_straps_prod	11.588m	11.891ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.935m	3.280ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.502m	8.729ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.094m	6.009ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.094m	6.009ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.242m	6.896ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	31.622m	20.760ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.796m	3.964ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.205m	5.631ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.947m	19.025ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.162m	3.028ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.748m	5.677ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.417m	2.617ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.991m	9.626ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.745m	2.625ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.286m	5.304ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.263m	2.344ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.434m	3.047ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.840m	5.558ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.249m	5.114ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.936m	3.046ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.249m	5.114ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.873m	2.668ms	1	1	100.00
		chip_sw_aes_smoketest	1.993m	2.882ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.028m	2.753ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.964m	2.510ms	1	1	100.00
		chip_sw_csrng_smoketest	2.066m	2.852ms	1	1	100.00
		chip_sw_entropy_src_smoketest	6.007m	4.167ms	1	1	100.00
		chip_sw_gpio_smoketest	2.887m	3.385ms	1	1	100.00
		chip_sw_hmac_smoketest	2.745m	2.656ms	1	1	100.00
		chip_sw_kmac_smoketest	3.161m	3.181ms	1	1	100.00
		chip_sw_otbn_smoketest	16.178m	9.429ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.984m	6.888ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.576m	4.657ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.833m	2.390ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.586m	2.951ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.007m	2.550ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.295m	3.447ms	1	1	100.00
		chip_sw_uart_smoketest	2.804m	3.115ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.873m	3.142ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.169m	5.190ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.915h	59.833ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.429m	14.642ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.368m	4.482ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.211m	3.635ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.196m	3.472ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.833h	52.310ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.982h	56.126ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	48.050s	2.360ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	48.050s	2.360ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.152h	37.292ms	1	1	100.00
		chip_same_csr_outstanding	17.322m	14.372ms	1	1	100.00
		chip_csr_hw_reset	3.667m	6.017ms	1	1	100.00
		chip_csr_rw	3.259m	3.879ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.152h	37.292ms	1	1	100.00
		chip_same_csr_outstanding	17.322m	14.372ms	1	1	100.00
		chip_csr_hw_reset	3.667m	6.017ms	1	1	100.00
		chip_csr_rw	3.259m	3.879ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	13.240s	241.739us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.090s	49.824us	1	1	100.00
		xbar_smoke_large_delays	58.280s	9.432ms	1	1	100.00
		xbar_smoke_slow_rsp	24.130s	2.690ms	1	1	100.00
		xbar_random_zero_delays	23.470s	233.075us	1	1	100.00
		xbar_random_large_delays	5.135m	55.578ms	1	1	100.00
		xbar_random_slow_rsp	4.580m	33.458ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	17.140s	637.339us	1	1	100.00
		xbar_error_and_unmapped_addr	33.050s	1.443ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	9.220s	163.730us	1	1	100.00
		xbar_error_and_unmapped_addr	33.050s	1.443ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	35.900s	1.384ms	1	1	100.00
		xbar_access_same_device_slow_rsp	1.732m	12.785ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	21.740s	472.603us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.888m	8.634ms	1	1	100.00
		xbar_stress_all_with_error	1.676m	2.386ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.707m	5.773ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.259m	203.084us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.429m	14.642ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	31.359m	25.889ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.962m	15.205ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.366m	11.870ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.149m	15.565ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.840m	15.539ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.523m	15.280ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	37.540m	15.165ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.320s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	27.570s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	26.990s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	28.500s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.760s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.970s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	28.070s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.550s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.340s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.870s	10.400us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	24.670s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.200s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.350s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.430s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.240s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.560s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.120s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.800s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.490s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.520s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.300s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.110s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.850s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.240s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.980s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.528m	11.418ms	1	1	100.00
		rom_e2e_asm_init_dev	37.721m	15.739ms	1	1	100.00
		rom_e2e_asm_init_prod	38.058m	15.543ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.007m	15.545ms	1	1	100.00
		rom_e2e_asm_init_rma	36.165m	15.654ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	37.762m	14.348ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.479m	14.593ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.432m	14.864ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.780m	15.986ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.480m	18.204ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.480m	18.204ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.862m	2.876ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.162m	3.028ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.526m	3.085ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.681m	2.261ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	13.401m	7.950ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.881m	2.371ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.974m	5.150ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.766m	5.632ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.928m	6.285ms	1	1	100.00
		chip_plic_all_irqs_10	4.870m	3.775ms	1	1	100.00
		chip_plic_all_irqs_20	5.601m	3.576ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.069m	3.032ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.986m	14.873ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	5.315m	5.463ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.651m	2.811ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.721m	10.091ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.662m	9.497ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.008m	8.002ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.737m	8.116ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.270h	256.176ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.332m	4.733ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.984m	6.888ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.332m	4.733ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.924m	8.805ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.924m	8.805ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.317m	6.029ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.436m	5.429ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.232m	6.125ms	1	1	100.00
		chip_sw_aes_idle	2.681m	2.261ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.133m	2.586ms	1	1	100.00
		chip_sw_kmac_idle	2.522m	3.458ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.054m	5.074ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.034m	3.786ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.113m	4.381ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.777m	3.703ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.812m	9.399ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.974m	3.371ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.866m	4.536ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.512m	3.632ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.345m	4.791ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.265m	3.524ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.250m	4.388ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.242m	6.896ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.768m	5.848ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.512m	3.632ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.345m	4.791ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.796m	3.964ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.205m	5.631ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.947m	19.025ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.162m	3.028ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.748m	5.677ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.417m	2.617ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.991m	9.626ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.745m	2.625ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.286m	5.304ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.263m	2.344ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.857m	2.541ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.552m	4.511ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.515m	7.610ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.279m	25.643ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.610m	3.103ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.252m	2.828ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.554m	8.617ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.102m	2.880ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.567m	4.714ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.182m	22.894ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	41.297m	27.174ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.242m	6.896ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.107m	4.828ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.127m	4.102ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.766m	5.632ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	18.662m	9.497ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.981m	5.321ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.103m	2.989ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.134m	7.230ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.444m	3.187ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	58.549m	22.584ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.474m	2.084ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.580m	7.035ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.474m	2.084ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.981m	5.321ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.123m	2.614ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.823m	20.336ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.598m	4.892ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.205m	5.631ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.436m	4.188ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.796m	3.964ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	54.919m	44.397ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.823m	20.336ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.069m	3.760ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.384m	10.056ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.462m	3.814ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	54.919m	44.397ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.462m	3.814ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.462m	3.814ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.462m	3.814ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.462m	3.814ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.766m	5.632ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.688m	8.253ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.345m	5.607ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.103m	5.940ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.103m	5.940ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.657m	3.080ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.417m	2.617ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.133m	2.586ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.752m	2.814ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.437m	7.549ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.258m	4.953ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.107m	5.409ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.016m	4.336ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.708m	4.048ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.384m	10.056ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.991m	9.626ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	11.497m	7.057ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	13.401m	7.950ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	34.622m	11.519ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.398m	2.464ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.737m	2.756ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.745m	2.625ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.384m	10.056ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.158m	13.654ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.350m	2.746ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.665m	8.299ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.522m	3.458ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.974m	5.150ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.793m	2.661ms	1	1	100.00
		chip_tap_straps_rma	3.391m	3.846ms	1	1	100.00
		chip_tap_straps_prod	11.588m	11.891ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.890m	2.881ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.158m	13.654ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.158m	13.654ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.158m	13.654ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.103m	8.349ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.462m	3.814ms	1	1	100.00
		chip_sw_flash_rma_unlocked	54.919m	44.397ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.658m	3.120ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.863m	6.517ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.096m	6.459ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.268m	5.634ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.158m	13.654ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.384m	10.056ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.518m	8.789ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.542m	9.767ms	1	1	100.00
		chip_prim_tl_access	3.688m	8.253ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.768m	5.848ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.974m	3.371ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.866m	4.536ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.512m	3.632ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.345m	4.791ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.265m	3.524ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.250m	4.388ms	1	1	100.00
		chip_tap_straps_dev	1.793m	2.661ms	1	1	100.00
		chip_tap_straps_rma	3.391m	3.846ms	1	1	100.00
		chip_tap_straps_prod	11.588m	11.891ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.046m	11.855ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.739m	3.944ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.772m	3.341ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.407m	3.750ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.517m	3.820ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.580m	24.058ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.046m	11.855ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.031h	45.297ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.062h	46.215ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.828m	8.606ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.046h	46.387ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	17.580m	24.058ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.371m	2.101ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.227m	3.030ms	1	1	100.00
		rom_volatile_raw_unlock	1.109m	2.477ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.850m	17.403ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.947m	19.025ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.232m	6.125ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.232m	6.125ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.232m	6.125ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.365m	3.320ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.158m	13.654ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.823m	20.336ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.365m	3.320ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.384m	10.056ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.697m	4.254ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.770m	2.671ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.823m	20.336ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.365m	3.320ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.384m	10.056ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.697m	4.254ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.770m	2.671ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.158m	13.654ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.099m	4.865ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.890m	2.881ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.658m	3.120ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.863m	6.517ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.096m	6.459ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.268m	5.634ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.158m	13.654ms	1	1	100.00
		chip_prim_tl_access	3.688m	8.253ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.688m	8.253ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.021m	9.258ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.408m	7.685ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.530m	24.644ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.684m	7.490ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.431m	9.721ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.603m	7.416ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.833m	22.140ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.761m	15.089ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	5.924m	8.805ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.592m	11.513ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.390m	5.628ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.408m	7.685ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.585m	4.154ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	37.228m	41.273ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.618m	7.290ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.415m	3.759ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.603m	21.373ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.977m	7.058ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.289m	9.380ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.046m	30.666ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.204m	3.219ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.766m	5.632ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.518m	8.789ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.518m	8.789ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.289m	9.380ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.603m	21.373ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.390m	5.628ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.984m	6.888ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.659m	5.336ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.494m	4.953ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.060m	4.037ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.986m	14.873ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.154m	1.986ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.766m	5.632ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.008m	8.002ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.673m	5.328ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.421m	4.289ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.026m	2.224ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.770m	2.671ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.494m	4.953ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.494m	4.953ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	9.052m	9.963ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.006m	13.553ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.659m	5.336ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.127m	5.817ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	6.076m	6.445ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.391m	3.846ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.046m	11.855ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.928m	6.285ms	1	1	100.00
		chip_plic_all_irqs_10	4.870m	3.775ms	1	1	100.00
		chip_plic_all_irqs_20	5.601m	3.576ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.212m	2.783ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.393m	2.191ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.429m	14.642ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.737m	7.888ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.456m	3.641ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.967m	3.257ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.609m	2.739ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.697m	4.254ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.286m	5.304ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.387m	8.588ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.368m	8.460ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.542m	9.767ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.766m	5.632ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.094m	6.009ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.977m	7.058ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.508m	22.356ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.558m	2.829ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.414m	3.449ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.792m	4.797ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.508m	22.356ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.508m	22.356ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	13.183m	11.903ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	13.183m	11.903ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.656m	4.687ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.480m	18.204ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.482m	2.660ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.811m	2.858ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.679m	3.693ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.513m	4.264ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.001m	8.306ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.248h	31.268ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.881m	12.824ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.136m	2.828ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.373m	2.559ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.145m	3.699ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.464h	71.614ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.947m	3.705ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.130m	11.272ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.650m	11.301ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.264m	11.943ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.029m	4.217ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.248m	3.825ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.062m	4.527ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	23.271s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.549m	4.985ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.585m	3.174ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.847m	4.300ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	21.193m	10.161ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.400m	2.933ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.408m	4.895ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.177m	2.295ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.888m	4.695ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.645m	5.561ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.078m	4.169ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.289m	9.380ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.130m	11.272ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.650m	11.301ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.264m	11.943ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.276m	6.006ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.766m	5.632ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.389h	38.246ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.389h	38.246ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.214m	3.573ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.779m	4.018ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	45.130m	19.140ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.890m	2.919ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.984m	5.700ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.271m	3.045ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.488m	2.465ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.450m	3.575ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.511s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.757m	3.212ms	1	1	100.00
		TOTAL			287	325	88.31

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.23026722625597422175544462110581850395681111300976539001205736301436222755988
    Line 716, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.112545537608090521413154743406691723192888602822218462258994064117080121392116
    Line 681, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.109850123459470241764593368395279876866124205423277758366471578470914728658253
    Line 746, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.39181066043210828071612254358523370012504302352355586266173286536977770241195
    Line 636, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.18737462359429626831481174787013904351558938016935582696418888505248287894528
    Line 642, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.12409547700572266749961867334847375830207519852679933069217007756088693210635
    Line 674, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.5421644298810465079806088149947711927006923670389756726396440837505283412315
    Line 653, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.87398490580999841696601220321151162710034977003198610828696527468423785711444
    Line 691, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.110976926207103116685598129357141684446420339042801760815320853363768198535720
    Line 681, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.95418522872513064853035475713964333918236958038332834407581902923233017626044
    Line 709, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.114720041376014253357982204265604292788120757438291981471219473005182781236569
    Line 779, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.72926464499144408736187368720193169347541019784657676759517354018806215750125
    Line 707, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.62022665821301764218406255854537634601061798638122761200313211468790253540614
    Line 722, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.89312191614777899877920070285007026571161134097444966209005226842673190292306
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.459s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.107356244539501801497032173509273950440282852722548107978384031030111759122619
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 13.631s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.89210014942946064303079064940495583596987651043205497360968164010646317019489
    Line 807, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.24989752640445882042238222477295085867767214056411743619208207508903473830846
    Line 586, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.102460974932895376817069673391592446790266158748815501779773937041803221235112
    Line 929, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.41809098765060937170594964021174033224466660732303926026551702283635236513505
    Line 807, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.75450135902679677461369173885240831998101391683590106471730431767138865023037
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3640.695380 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3640.695380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@94045) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.85252540237728490285881550928308150667455104792187172840508780551322126109857
Line 441, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4953.493064 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@94045) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4953.493064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.11205088419599516990507666861248371370819761758410463604702770885006551124072
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11903.160800 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11903.160800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.87448977735080711662507447117084696492143252767344759149033062526806425346568
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2370.591950 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2370.591950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.42278408186064446133534169175285229328568850532642383840834596324473493759168
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2810.706160 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2810.706160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:586) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.115720832157197524677591169736883748879743087757175949993897003494317114922781
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2989.057535 us: (cip_base_vseq.sv:586) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2989.057535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32139) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.3938744721885893540414895308120077667047991054985747219362287834941663271780
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2360.111108 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32139) { a_addr: 'h10704  a_data: 'h884910d3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h19530  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2360.111108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.88602603535517814284476765710458592794477076410555758190730793869222943332523
    Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3635.460000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3635.460000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.115604590354681057939615182488402711805986105620993402045225085279972555639442
    Line 442, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3472.380500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3472.380500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.100316786175808091791032675549572965767899706916907843150223946156033932230429
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 20759.534015 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 20759.534015 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.47371437751470803332007747574947117400144107004892884187584924017758593743394
    Line 461, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3705.108869 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3705.108869 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.93509717793322248516709749618210840504794377061232753913973575020493804962855
    Line 782, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.104493800070375834984616587296234831208282415428738243435612658516019492216664
    Line 791, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```