ADC_CTRL Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.260s	5.985ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.940s	978.159us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.530s	531.499us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	15.490s	31.654ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.760s	681.414us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.480s	417.920us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.530s	531.499us	1	1	100.00
		adc_ctrl_csr_aliasing	2.760s	681.414us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.367m	325.915ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.939m	485.351ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.656m	325.149ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	5.061m	167.212ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.200s	168.139ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	15.969m	620.692ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	3.944m	599.290ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.860s	1.437ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	4.620s	3.557ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	48.400s	27.288ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	53.070s	107.581ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	8.740m	676.218ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.850s	431.018us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.230s	453.873us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.010s	858.554us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.010s	858.554us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.940s	978.159us	1	1	100.00
		adc_ctrl_csr_rw	2.530s	531.499us	1	1	100.00
		adc_ctrl_csr_aliasing	2.760s	681.414us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.560s	2.141ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.940s	978.159us	1	1	100.00
		adc_ctrl_csr_rw	2.530s	531.499us	1	1	100.00
		adc_ctrl_csr_aliasing	2.760s	681.414us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.560s	2.141ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	5.780s	8.124ms	1	1	100.00
		adc_ctrl_tl_intg_err	10.850s	9.055ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	10.850s	9.055ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.060s	1.072ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.58256276092668238643609040550651668397777652154027766079986381183705878538922
      Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 1436905284 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 1436905284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---