CSRNG Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	83.348us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	180.686us	1	1	100.00
V1	csr_rw	csrng_csr_rw	5.000s	22.653us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	12.000s	475.643us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	35.025us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	27.931us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	22.653us	1	1	100.00
		csrng_csr_aliasing	5.000s	35.025us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	9.000s	203.677us	1	1	100.00
V2	alerts	csrng_alert	12.000s	518.558us	1	1	100.00
V2	err	csrng_err	5.000s	20.516us	1	1	100.00
V2	cmds	csrng_cmds	1.900m	9.626ms	1	1	100.00
V2	life cycle	csrng_cmds	1.900m	9.626ms	1	1	100.00
V2	stress_all	csrng_stress_all	2.483m	3.748ms	1	1	100.00
V2	intr_test	csrng_intr_test	5.000s	24.056us	1	1	100.00
V2	alert_test	csrng_alert_test	5.000s	40.891us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	6.000s	50.427us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	6.000s	50.427us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	180.686us	1	1	100.00
		csrng_csr_rw	5.000s	22.653us	1	1	100.00
		csrng_csr_aliasing	5.000s	35.025us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	27.956us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	180.686us	1	1	100.00
		csrng_csr_rw	5.000s	22.653us	1	1	100.00
		csrng_csr_aliasing	5.000s	35.025us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	27.956us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	tl_intg_err	csrng_sec_cm	9.000s	464.514us	1	1	100.00
		csrng_tl_intg_err	9.000s	553.257us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	103.439us	1	1	100.00
		csrng_csr_rw	5.000s	22.653us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	12.000s	518.558us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	2.483m	3.748ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
		csrng_sec_cm	9.000s	464.514us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
		csrng_sec_cm	9.000s	464.514us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
		csrng_sec_cm	9.000s	464.514us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
		csrng_sec_cm	9.000s	464.514us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
		csrng_sec_cm	9.000s	464.514us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
		csrng_sec_cm	9.000s	464.514us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
		csrng_sec_cm	9.000s	464.514us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	12.000s	518.558us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	2.483m	3.748ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	12.000s	518.558us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	553.257us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
		csrng_sec_cm	9.000s	464.514us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
		csrng_sec_cm	9.000s	464.514us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	203.677us	1	1	100.00
		csrng_err	5.000s	20.516us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	4.000s	27.972us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.93363813177690520952479193064800512015543165060744792507493020594095403446754
      Line 117, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  27971621 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
        UVM_INFO @  27971621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---