EDN Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.900s 181.362us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.660s 107.777us 1 1 100.00
V1 csr_rw edn_csr_rw 1.680s 15.778us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.080s 56.208us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.990s 45.826us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.810s 18.509us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.680s 15.778us 1 1 100.00
edn_csr_aliasing 1.990s 45.826us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.210s 47.213us 1 1 100.00
V2 csrng_commands edn_genbits 2.210s 47.213us 1 1 100.00
V2 genbits edn_genbits 2.210s 47.213us 1 1 100.00
V2 interrupts edn_intr 1.770s 24.582us 1 1 100.00
V2 alerts edn_alert 1.850s 28.465us 1 1 100.00
V2 errs edn_err 1.910s 19.969us 1 1 100.00
V2 disable edn_disable 1.690s 17.491us 1 1 100.00
edn_disable_auto_req_mode 1.910s 43.378us 1 1 100.00
V2 stress_all edn_stress_all 3.770s 555.899us 1 1 100.00
V2 intr_test edn_intr_test 1.720s 28.851us 1 1 100.00
V2 alert_test edn_alert_test 1.620s 14.245us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.520s 143.329us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.520s 143.329us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.660s 107.777us 1 1 100.00
edn_csr_rw 1.680s 15.778us 1 1 100.00
edn_csr_aliasing 1.990s 45.826us 1 1 100.00
edn_same_csr_outstanding 2.020s 64.164us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.660s 107.777us 1 1 100.00
edn_csr_rw 1.680s 15.778us 1 1 100.00
edn_csr_aliasing 1.990s 45.826us 1 1 100.00
edn_same_csr_outstanding 2.020s 64.164us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.400s 474.013us 1 1 100.00
edn_tl_intg_err 2.250s 186.679us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.860s 37.270us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.850s 28.465us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.400s 474.013us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.400s 474.013us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.400s 474.013us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.400s 474.013us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.850s 28.465us 1 1 100.00
edn_sec_cm 6.400s 474.013us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.850s 28.465us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.250s 186.679us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets