HMAC Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.460s 4.852ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.630s 32.103us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.670s 192.539us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 13.610s 3.420ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.560s 647.088us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 5.274m 39.600ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.670s 192.539us 1 1 100.00
hmac_csr_aliasing 3.560s 647.088us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 17.660s 437.106us 1 1 100.00
V2 back_pressure hmac_back_pressure 40.660s 10.748ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.150s 246.461us 1 1 100.00
hmac_test_sha384_vectors 6.782m 12.208ms 1 1 100.00
hmac_test_sha512_vectors 20.860s 540.928us 1 1 100.00
hmac_test_hmac256_vectors 11.850s 571.585us 1 1 100.00
hmac_test_hmac384_vectors 11.960s 1.371ms 1 1 100.00
hmac_test_hmac512_vectors 11.670s 647.321us 1 1 100.00
V2 burst_wr hmac_burst_wr 24.460s 5.850ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 6.496m 6.423ms 1 1 100.00
V2 error hmac_error 1.569m 43.471ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.915m 8.589ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.460s 4.852ms 1 1 100.00
hmac_long_msg 17.660s 437.106us 1 1 100.00
hmac_back_pressure 40.660s 10.748ms 1 1 100.00
hmac_datapath_stress 6.496m 6.423ms 1 1 100.00
hmac_burst_wr 24.460s 5.850ms 1 1 100.00
hmac_stress_all 37.540s 1.016ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.460s 4.852ms 1 1 100.00
hmac_long_msg 17.660s 437.106us 1 1 100.00
hmac_back_pressure 40.660s 10.748ms 1 1 100.00
hmac_datapath_stress 6.496m 6.423ms 1 1 100.00
hmac_wipe_secret 1.915m 8.589ms 1 1 100.00
hmac_test_sha256_vectors 9.150s 246.461us 1 1 100.00
hmac_test_sha384_vectors 6.782m 12.208ms 1 1 100.00
hmac_test_sha512_vectors 20.860s 540.928us 1 1 100.00
hmac_test_hmac256_vectors 11.850s 571.585us 1 1 100.00
hmac_test_hmac384_vectors 11.960s 1.371ms 1 1 100.00
hmac_test_hmac512_vectors 11.670s 647.321us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.460s 4.852ms 1 1 100.00
hmac_long_msg 17.660s 437.106us 1 1 100.00
hmac_back_pressure 40.660s 10.748ms 1 1 100.00
hmac_datapath_stress 6.496m 6.423ms 1 1 100.00
hmac_burst_wr 24.460s 5.850ms 1 1 100.00
hmac_error 1.569m 43.471ms 1 1 100.00
hmac_wipe_secret 1.915m 8.589ms 1 1 100.00
hmac_test_sha256_vectors 9.150s 246.461us 1 1 100.00
hmac_test_sha384_vectors 6.782m 12.208ms 1 1 100.00
hmac_test_sha512_vectors 20.860s 540.928us 1 1 100.00
hmac_test_hmac256_vectors 11.850s 571.585us 1 1 100.00
hmac_test_hmac384_vectors 11.960s 1.371ms 1 1 100.00
hmac_test_hmac512_vectors 11.670s 647.321us 1 1 100.00
hmac_stress_all 37.540s 1.016ms 1 1 100.00
V2 stress_all hmac_stress_all 37.540s 1.016ms 1 1 100.00
V2 alert_test hmac_alert_test 1.560s 55.761us 1 1 100.00
V2 intr_test hmac_intr_test 1.490s 85.177us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.510s 139.962us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.510s 139.962us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.630s 32.103us 1 1 100.00
hmac_csr_rw 1.670s 192.539us 1 1 100.00
hmac_csr_aliasing 3.560s 647.088us 1 1 100.00
hmac_same_csr_outstanding 2.170s 81.973us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.630s 32.103us 1 1 100.00
hmac_csr_rw 1.670s 192.539us 1 1 100.00
hmac_csr_aliasing 3.560s 647.088us 1 1 100.00
hmac_same_csr_outstanding 2.170s 81.973us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.470s 428.441us 1 1 100.00
hmac_tl_intg_err 4.590s 811.655us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.590s 811.655us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.460s 4.852ms 1 1 100.00
V3 stress_reset hmac_stress_reset 4.100s 59.789us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 4.391m 11.295ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 5.440s 1.084ms 1 1 100.00
TOTAL 28 28 100.00