I2C Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	12.980s	1.379ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.580s	516.927us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.560s	20.994us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.570s	25.563us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.590s	530.898us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.930s	220.717us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.860s	28.319us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.570s	25.563us	1	1	100.00
		i2c_csr_aliasing	1.930s	220.717us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.660s	1.337ms	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	6.740m	100.150ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	4.850s	1.409ms	1	1	100.00
V2	host_override	i2c_host_override	1.680s	39.832us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.225m	19.182ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.449m	4.107ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.790s	107.759us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.270s	1.544ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.120s	417.050us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	45.270s	10.730ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.530s	3.055ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.000s	661.034us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.070s	11.516ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	7.615m	43.911ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.920s	3.718ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	14.190s	1.434ms	1	1	100.00
		i2c_target_intr_smoke	5.500s	4.541ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.790s	147.799us	1	1	100.00
		i2c_target_fifo_reset_tx	1.500s	149.663us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.253m	36.216ms	1	1	100.00
		i2c_target_stress_rd	14.190s	1.434ms	1	1	100.00
		i2c_target_intr_stress_wr	32.040s	15.716ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.060s	2.097ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	7.050s	955.214us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.650s	11.381ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	19.930s	10.149ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.290s	5.606ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.930s	304.585us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.850s	1.409ms	1	1	100.00
		i2c_host_perf_precise	1.810s	76.403us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.530s	3.055ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.890s	151.580us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.040s	1.069ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.930s	593.290us	1	1	100.00
		i2c_target_nack_txstretch	1.970s	142.224us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.220s	1.517ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.380s	484.310us	1	1	100.00
V2	alert_test	i2c_alert_test	1.430s	172.001us	1	1	100.00
V2	intr_test	i2c_intr_test	1.460s	48.386us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.270s	79.610us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.270s	79.610us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.560s	20.994us	1	1	100.00
		i2c_csr_rw	1.570s	25.563us	1	1	100.00
		i2c_csr_aliasing	1.930s	220.717us	1	1	100.00
		i2c_same_csr_outstanding	1.690s	152.659us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.560s	20.994us	1	1	100.00
		i2c_csr_rw	1.570s	25.563us	1	1	100.00
		i2c_csr_aliasing	1.930s	220.717us	1	1	100.00
		i2c_same_csr_outstanding	1.690s	152.659us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	1.910s	137.812us	1	1	100.00
		i2c_sec_cm	1.660s	154.335us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.910s	137.812us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	2.860s	309.948us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.140s	817.877us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	19.630s	1.848ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:924) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.8117348826690983413275444502122397822808541189729332496921165576280694355167
      Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 309947956 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 309947956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.44977009108039512912455737968665813394929939155901088981704455715864930580774
      Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1848332432 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1848332432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.100769346424496702288424597461797767310364871754724129097245565576133069883806
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 817876830 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 162 [0xa2])
        UVM_INFO @ 817876830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.3396235343629050091387687942240235232049335333318466887609536319965422455973
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10149257722 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10149257722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---