KEYMGR Simulation Results

Thursday April 17 2025 20:22:04 UTC

GitHub Revision: 91d1222

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	7.770s	407.995us	1	1	100.00
V1	random	keymgr_random	4.630s	2.160ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.740s	64.954us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.610s	10.021us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.210s	1.796ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.240s	878.846us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.120s	203.677us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.610s	10.021us	0	1	0.00
		keymgr_csr_aliasing	8.240s	878.846us	0	1	0.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	3.600s	104.156us	1	1	100.00
V2	sideload	keymgr_sideload	2.980s	230.890us	1	1	100.00
		keymgr_sideload_kmac	3.390s	289.207us	1	1	100.00
		keymgr_sideload_aes	2.860s	232.888us	1	1	100.00
		keymgr_sideload_otbn	2.870s	57.773us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.930s	77.676us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.800s	33.164us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.480s	500.723us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.940s	736.312us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.350s	312.660us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.850s	186.552us	1	1	100.00
V2	stress_all	keymgr_stress_all	21.310s	1.001ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.570s	18.771us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.710s	17.733us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.150s	166.090us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.150s	166.090us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.740s	64.954us	1	1	100.00
		keymgr_csr_rw	1.610s	10.021us	0	1	0.00
		keymgr_csr_aliasing	8.240s	878.846us	0	1	0.00
		keymgr_same_csr_outstanding	2.300s	51.908us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.740s	64.954us	1	1	100.00
		keymgr_csr_rw	1.610s	10.021us	0	1	0.00
		keymgr_csr_aliasing	8.240s	878.846us	0	1	0.00
		keymgr_same_csr_outstanding	2.300s	51.908us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
		keymgr_tl_intg_err	1.980s	33.153us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.050s	592.673us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.050s	592.673us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.050s	592.673us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.050s	592.673us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	10.470s	878.833us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.980s	33.153us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.050s	592.673us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.600s	104.156us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.630s	2.160ms	1	1	100.00
		keymgr_csr_rw	1.610s	10.021us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.630s	2.160ms	1	1	100.00
		keymgr_csr_rw	1.610s	10.021us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.630s	2.160ms	1	1	100.00
		keymgr_csr_rw	1.610s	10.021us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.800s	33.164us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.350s	312.660us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.350s	312.660us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.630s	2.160ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.690s	42.540us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.770s	93.695us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.800s	33.164us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.770s	93.695us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.770s	93.695us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.770s	93.695us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.440s	489.980us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.770s	93.695us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.290s	2.910ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.43895752235229848925586735718056154281528975865380641350639948482613326994238
      Line 94, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @  33152939 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @  33152939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.13246596954237038463930755683300404632107588146966725937223113436095249118098
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
        UVM_ERROR @  10020906 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
        UVM_INFO @  10020906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.35989066559250527585035401836227967897565536073962271842054846356150608795965
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
        UVM_ERROR @ 878846387 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
        UVM_INFO @ 878846387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---